coreboot-gerrit June 2018

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Change in coreboot[master]: cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27090 ) Change subject: cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74856/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28958/ : SUCCESS -- To view, visit https://review.coreboot.org/27090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738 Gerrit-Change-Number: 27090 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 13:56:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]src/cpu/intel/car: Update microcode before setting up CARe
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27091 Change subject: [WIP]src/cpu/intel/car: Update microcode before setting up CARe ...................................................................... [WIP]src/cpu/intel/car: Update microcode before setting up CARe This reuses cbfstool adding a FIT table with pointers to microcode headers meant for later Intel CPUs. Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S A src/cpu/intel/microcode/microcode.S M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc 4 files changed, 157 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/27091/1 diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S b/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S index 351f98c..40b7733 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S @@ -28,13 +28,9 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -.global bootblock_pre_c_entry +.global setup_car - -.code32 -bootblock_pre_c_entry: -_cache_as_ram_setup: - +setup_car: cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/microcode/microcode.S b/src/cpu/intel/microcode/microcode.S new file mode 100644 index 0000000..5114069 --- /dev/null +++ b/src/cpu/intel/microcode/microcode.S @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/post_code.h> + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: +_update_bsp_microcode: + + /* Follow the _FIT_ pointer */ + movl $0xffffffc0, %edi + cmpl $0, (%edi) + je end_microcode_update + /* %edi points at the start of the FIT table */ + movl (%edi), %eax + movl %eax, %edi + +check_fit_header: + /* Check if the FIT table starts with "_FIT_ " */ + movl 0(%edi), %ebx + cmpl %ebx, fit_header + jne end_microcode_update + movl 4(%edi), %ebx + cmpl %ebx, fit_header+4 + jne end_microcode_update + +check_fit_entry_checksum_valid: + movb 14(%edi), %bl + cmpb $0x80, %bl + jne end_microcode_update + +check_fit_checksum: + /* All bytes of the table must add up to a 0 byte */ + movl 8(%edi), %ecx + shl $4, %ecx + movl %edi, %esi + movb $0, %al + +1: + movb (%esi), %dl + addb %dl, %al + inc %esi + dec %ecx + jnz 1b + + cmp $0, %al + + jne end_microcode_update + + mov $CONFIG_CPU_INTEL_NUM_FIT_ENTRIES, %ecx + +/* + * The microcode header is 24 bytes wide and has the following + * structure: + * Header Version : 32bit + * Update Revision : 32bit + * Date : 32bit + * Processor Signature : 32bit + * Checksum : 32bit + * Loader Revision : 32bit + * Processor Flags : 32bit + * Data Size : 32bit + * Total Size : 32bit + * Reserved : 96bit + * + * We only check if the Processor signature and flags match and check + * if the revision of the update is newer than what is installed + */ + +check_microcode_entry: + /* Save %ecx for loop, we need it for wrmsr */ + movl %ecx, %ebp + + /* Go to the next FIT entry */ + add $16, %edi + /* empty entry */ + cmpl $0, (%edi) + je end_microcode_update + /* Check fit entry for microcode type */ + + cmpb $0x01, 14(%edi) + jne end_microcode_update + + /* ESI holds the microcode pointer */ + movl 0(%edi), %esi + + /* Processor family+model signature=cpuid_eax(1) */ + movl $1, %eax + cpuid + cmpl 12(%esi), %eax + jne next_entry + + /* Processor flags + rdmsr 0x17 + pf = 1 << ((msr.hi >> 18) & 7) */ + movl $0x17, %ecx + rdmsr + shr $18, %edx + andl $7, %edx + movl $1, %eax + /* needs to be %cl for shl */ + mov %edx, %ecx + shl %cl, %eax + cmpl %eax, 24(%esi) + jnz next_entry + + /* Check if revision is higher than current */ + movl $0x8b, %ecx + rdmsr + cmpl 4(%esi), %edx + /* Don't upgrade if already greater or equal */ + jge end_microcode_update + + /* do actual update */ + mov %esi, %eax + add $48, %eax + xorl %edx, %edx + movl $0x79, %ecx + wrmsr + + jmp end_microcode_update + +next_entry: + movl %ebp, %ecx + dec %ecx + jnz check_microcode_entry + + +end_microcode_update: + jmp setup_car + +_update_bsp_microcode_end: + +fit_header: + .ascii "_FIT_ " diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 9fec0d2..98d73d0 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -14,6 +14,11 @@ select MMX select SSE select SIPI_VECTOR_IN_ROM + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + +config CPU_INTEL_NUM_FIT_ENTRIES + int + default 45 config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index a37a1ca..34afb74 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -16,6 +16,7 @@ ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S else +bootblock-y += ../microcode/microcode.S bootblock-y += ../car/p4-netburst/cache_as_ram_bootblock.S bootblock-y += ../car/bootblock.c endif -- To view, visit https://review.coreboot.org/27091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Gerrit-Change-Number: 27091 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27090 Change subject: cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header ...................................................................... cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header Some older CPUs have a fixed size of 2048 bytes for microcode total size. Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/27090/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index e3e6c32..1684ef6 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -226,13 +226,14 @@ mcu_header = rom_buffer_pointer(&image->buffer, current_offset); - /* Quickly sanity check a prospective microcode update. */ - if (mcu_header->total_size < sizeof(*mcu_header)) - break; + /* Newer microcode updates include a size field, whereas older + * containers set it at 0 and are exactly 2048 bytes long */ + uint32_t update_size = mcu_header->total_size + ? mcu_header->total_size : 2048; /* FIXME: Should the checksum be validated? */ mcus[num_mcus].offset = current_offset; - mcus[num_mcus].size = mcu_header->total_size; + mcus[num_mcus].size = update_size; /* Proceed to next payload. */ current_offset += mcus[num_mcus].size; -- To view, visit https://review.coreboot.org/27090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738 Gerrit-Change-Number: 27090 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/asus/p5g41t-m_lx: Add mainboard (not for merge yet)
by Angel Pons (Code Review) 13 Jun '18

13 Jun '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/27089 Change subject: mb/asus/p5g41t-m_lx: Add mainboard (not for merge yet) ...................................................................... mb/asus/p5g41t-m_lx: Add mainboard (not for merge yet) This board has an easy to access DIP8 socket. Most of the code comes from mb/intel/dg41wv, since it has the same chipset (x4x, ich7, w83627dhg). What is tested and works: * S3 resume * Some USB and SATA (only some have been tested) * Ethernet * Flashing coreboot internally from vendor BIOS. What does not work: * iGPU with 533 MHz dual DIMMs, display fails to light up on Linux Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asus/p5g41t-m_lx/Kconfig A src/mainboard/asus/p5g41t-m_lx/Kconfig.name A src/mainboard/asus/p5g41t-m_lx/Makefile.inc A src/mainboard/asus/p5g41t-m_lx/acpi/ec.asl A src/mainboard/asus/p5g41t-m_lx/acpi/ich7_pci_irqs.asl A src/mainboard/asus/p5g41t-m_lx/acpi/platform.asl A src/mainboard/asus/p5g41t-m_lx/acpi/superio.asl A src/mainboard/asus/p5g41t-m_lx/acpi/x4x_pci_irqs.asl A src/mainboard/asus/p5g41t-m_lx/acpi_tables.c A src/mainboard/asus/p5g41t-m_lx/board_info.txt A src/mainboard/asus/p5g41t-m_lx/cmos.default A src/mainboard/asus/p5g41t-m_lx/cmos.layout A src/mainboard/asus/p5g41t-m_lx/cstates.c A src/mainboard/asus/p5g41t-m_lx/devicetree.cb A src/mainboard/asus/p5g41t-m_lx/dsdt.asl A src/mainboard/asus/p5g41t-m_lx/gma-mainboard.ads A src/mainboard/asus/p5g41t-m_lx/gpio.c A src/mainboard/asus/p5g41t-m_lx/hda_verb.c A src/mainboard/asus/p5g41t-m_lx/romstage.c 19 files changed, 929 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27089/1 diff --git a/src/mainboard/asus/p5g41t-m_lx/Kconfig b/src/mainboard/asus/p5g41t-m_lx/Kconfig new file mode 100644 index 0000000..2d428d7 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/Kconfig @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz> +## Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P5G41T_M_LX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + #select PCIEXP_ASPM + #select PCIEXP_CLK_PM + #select PCIEXP_L1_SUB_STATE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_LIBGFXINIT + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MAINBOARD_DIR + string + default asus/p5g41t-m_lx + +config MAINBOARD_PART_NUMBER + string + default "P5G41T-M LX" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5G41T_M_LX diff --git a/src/mainboard/asus/p5g41t-m_lx/Kconfig.name b/src/mainboard/asus/p5g41t-m_lx/Kconfig.name new file mode 100644 index 0000000..e46d4b1 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5G41T_M_LX + bool "P5G41T-M LX" diff --git a/src/mainboard/asus/p5g41t-m_lx/Makefile.inc b/src/mainboard/asus/p5g41t-m_lx/Makefile.inc new file mode 100644 index 0000000..0786d6f --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/Makefile.inc @@ -0,0 +1,4 @@ +ramstage-y += cstates.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5g41t-m_lx/acpi/ec.asl b/src/mainboard/asus/p5g41t-m_lx/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5g41t-m_lx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5g41t-m_lx/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..18e1f00 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/acpi/ich7_pci_irqs.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + /* PCI1 SLOT 1 */ + Package() { 0x0003ffff, 0, 0, 0x14}, + Package() { 0x0003ffff, 1, 0, 0x15}, + Package() { 0x0003ffff, 2, 0, 0x16}, + Package() { 0x0003ffff, 3, 0, 0x17}, + + /* PCI1 SLOT 2 */ + Package() { 0x0004ffff, 0, 0, 0x15}, + Package() { 0x0004ffff, 1, 0, 0x16}, + Package() { 0x0004ffff, 2, 0, 0x17}, + Package() { 0x0004ffff, 3, 0, 0x14}, + }) +} Else { + Return (Package() { + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/asus/p5g41t-m_lx/acpi/platform.asl b/src/mainboard/asus/p5g41t-m_lx/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5g41t-m_lx/acpi/superio.asl b/src/mainboard/asus/p5g41t-m_lx/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5g41t-m_lx/acpi/x4x_pci_irqs.asl b/src/mainboard/asus/p5g41t-m_lx/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..5bec150 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, 0, 0x10 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 0x10 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 0x10 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 0x10 }, + Package() { 0x001cffff, 1, 0, 0x11 }, + Package() { 0x001cffff, 2, 0, 0x12 }, + Package() { 0x001cffff, 3, 0, 0x13 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 0x17 }, + Package() { 0x001dffff, 1, 0, 0x13 }, + Package() { 0x001dffff, 2, 0, 0x12 }, + Package() { 0x001dffff, 3, 0, 0x10 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, 0, 0x12 }, + Package() { 0x001fffff, 1, 0, 0x13 }, + }) + } Else { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/asus/p5g41t-m_lx/acpi_tables.c b/src/mainboard/asus/p5g41t-m_lx/acpi_tables.c new file mode 100644 index 0000000..d80fb4c --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/acpi_tables.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <stdint.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5g41t-m_lx/board_info.txt b/src/mainboard/asus/p5g41t-m_lx/board_info.txt new file mode 100644 index 0000000..17f2530 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5G41TM_LX/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5g41t-m_lx/cmos.default b/src/mainboard/asus/p5g41t-m_lx/cmos.default new file mode 100644 index 0000000..8aa2238 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=64M diff --git a/src/mainboard/asus/p5g41t-m_lx/cmos.layout b/src/mainboard/asus/p5g41t-m_lx/cmos.layout new file mode 100644 index 0000000..0a59868 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/cmos.layout @@ -0,0 +1,104 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +1024 144 r 0 recv_enable_results +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5g41t-m_lx/cstates.c b/src/mainboard/asus/p5g41t-m_lx/cstates.c new file mode 100644 index 0000000..128f655 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5g41t-m_lx/devicetree.cb b/src/mainboard/asus/p5g41t-m_lx/devicetree.cb new file mode 100644 index 0000000..358d65b --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/devicetree.cb @@ -0,0 +1,180 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> +# Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x8086 0x5756 + end + device pci 1.0 on end # PEG + device pci 2.0 on # Integrated graphics controller + subsystemid 0x8086 0x5756 + end + chip southbridge/intel/i82801gx # Southbridge + #register "pirqa_routing" = "0x0b" + #register "pirqb_routing" = "0x0b" + #register "pirqc_routing" = "0x0b" + #register "pirqd_routing" = "0x0b" + #register "pirqe_routing" = "0x80" + #register "pirqf_routing" = "0x80" + #register "pirqg_routing" = "0x80" + #register "pirqh_routing" = "0x0b" + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + #register "gpi0_routing" = "2" + #register "gpi1_routing" = "2" + #register "gpi2_routing" = "2" + #register "gpi3_routing" = "2" + #register "gpi4_routing" = "2" + #register "gpi5_routing" = "2" + #register "gpi6_routing" = "2" + #register "gpi7_routing" = "2" + #register "gpi8_routing" = "2" + #register "gpi9_routing" = "2" + #register "gpi10_routing" = "2" + #register "gpi11_routing" = "2" + #register "gpi12_routing" = "2" + #register "gpi13_routing" = "2" + #register "gpi14_routing" = "2" + #register "gpi15_routing" = "2" + + register "ide_enable_primary" = "0x1" + register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant + register "gpe0_en" = "0x440" + + device pci 1b.0 on # Audio + subsystemid 0x8086 0x5756 + end + device pci 1c.0 on end # (PCIEX1_1) + device pci 1c.1 on # PCIe 2: NIC + device pci 00.0 on + subsystemid 0x8086 0x5756 + end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on # USB + subsystemid 0x8086 0x5756 + end + device pci 1d.1 on # USB + subsystemid 0x8086 0x5756 + end + device pci 1d.2 on # USB + subsystemid 0x8086 0x5756 + end + device pci 1d.3 on # USB + subsystemid 0x8086 0x5756 + end + device pci 1d.7 on # USB + subsystemid 0x8086 0x5756 + end + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio Controller + device pci 1e.3 off end # AC'97 Modem Controller + device pci 1f.0 on # ISA bridge + subsystemid 0x8086 0x5756 + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + # global + irq 0x2c = 0xf2 + #floppy + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + drq 0x74 = 0x02 + end + device pnp 2e.1 on # Parallel port + # parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR (UNUSED?) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 on # GPIO5 + irq 0xe0 = 0xdf + irq 0xf3 = 0x09 # RSVD SUSLED settings + end + device pnp 2e.a on # ACPI + irq 0xe0 = 0x10 + irq 0xe1 = 0x0e + irq 0xe4 = 0x10 # Power dram during s3 + irq 0xe6 = 0x8c + end + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0x290 #0xa00 + irq 0x70 = 0 + end + device pnp 2e.c on # PECI, SST + irq 0xe0 = 0x10 + irq 0xe1 = 0x55 + end + end + end + device pci 1f.1 on end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x8086 0x5756 + end + device pci 1f.3 on # SMbus + subsystemid 0x8086 0x5756 + #chip drivers/i2c/ck505 + #register "mask" = "{ 0xff, 0xff, 0xff, + # 0xff, 0xff, 0xff, 0xff, 0xff, + # 0xff, 0xff, 0xff, 0xff, 0xff, + # 0xff, 0xff, 0xff, 0xff, 0xff, + # 0xff, 0xff, 0xff }" + #register "regs" = "{ 0x41, 0x99, 0xff, + # 0xff, 0xff, 0x00, 0x00, 0x06, + # 0x03, 0x65, 0x83, 0x80, 0x15, + # 0xc0, 0x09, 0x00, 0x00, 0x00, + # 0x06, 0x00, 0xea }" + #device i2c 69 on end + #end + end + end + end +end diff --git a/src/mainboard/asus/p5g41t-m_lx/dsdt.asl b/src/mainboard/asus/p5g41t-m_lx/dsdt.asl new file mode 100644 index 0000000..e11eb39 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5g41t-m_lx/gma-mainboard.ads b/src/mainboard/asus/p5g41t-m_lx/gma-mainboard.ads new file mode 100644 index 0000000..06511f9 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/gma-mainboard.ads @@ -0,0 +1,13 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p5g41t-m_lx/gpio.c b/src/mainboard/asus/p5g41t-m_lx/gpio.c new file mode 100644 index 0000000..0c19135 --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/gpio.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5g41t-m_lx/hda_verb.c b/src/mainboard/asus/p5g41t-m_lx/hda_verb.c new file mode 100644 index 0000000..23d566d --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x80865756, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01441130), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5g41t-m_lx/romstage.c b/src/mainboard/asus/p5g41t-m_lx/romstage.c new file mode 100644 index 0000000..234c59f --- /dev/null +++ b/src/mainboard/asus/p5g41t-m_lx/romstage.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> +#include <lib.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> +#include <device/pnp_def.h> +#include <timestamp.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +static void mb_lpc_setup(void) +{ + u32 reg32; + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Set GPIOs on superio, enable UART */ + pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x2c, 0x13); + + pnp_exit_ext_func_mode(SERIAL_DEV); + + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); + + reg32 = RCBA32(GCS); + reg32 |= (1 << 5); + RCBA32(GCS) = reg32; + RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD + | FD_ACAUD | FD_PATA | 1; + RCBA32(CG) = 0x00000001; +} + +static void ich7_enable_lpc(void) +{ + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); + /* Fixed IO decode ranges */ + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); + /* LPC enable devices */ + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + /* IO decode range: HWM on 0xa00 */ + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); +} + +void mainboard_romstage_entry(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + /* Set southbridge and Super I/O GPIOs. */ + ich7_enable_lpc(); + mb_lpc_setup(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); + +} -- To view, visit https://review.coreboot.org/27089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431 Gerrit-Change-Number: 27089 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

1 0

Change in coreboot[master]: src: Get rid of unneeded whitespace
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Get rid of unneeded whitespace ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28955/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74852/ : SUCCESS https://qa.coreboot.org/job/coreboot-toolchain/441/ : SUCCESS -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 11:23:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mediatek/mt8183: add pll and clock init support
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27031 ) Change subject: mediatek/mt8183: add pll and clock init support ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28956/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74854/ : SUCCESS -- To view, visit https://review.coreboot.org/27031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Gerrit-Change-Number: 27031 Gerrit-PatchSet: 4 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 11:12:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mediatek/mt8183: Add mtcmos init support
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27030 ) Change subject: mediatek/mt8183: Add mtcmos init support ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74853/ : SUCCESS -- To view, visit https://review.coreboot.org/27030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 Gerrit-Change-Number: 27030 Gerrit-PatchSet: 4 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 11:06:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Get rid of unneeded whitespace
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Get rid of unneeded whitespace ...................................................................... Patch Set 14: (21 comments) https://review.coreboot.org/#/c/26991/14/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/14/src/include/bootstate.h@127 PS14, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/bimini_fam10/rom… File src/mainboard/amd/bimini_fam10/romstage.c: https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/bimini_fam10/rom… PS14, Line 83: inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/ma… File src/mainboard/amd/tilapia_fam10/mainboard.c: https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/ma… PS14, Line 153: /* When the gpio40 is configured as GPIO, this will represent the output value*/ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/ma… PS14, Line 165: /* When the gpio40 is configured as GPIO, this will represent the output value*/ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/mainboard/asus/kfsn4-dre/resou… File src/mainboard/asus/kfsn4-dre/resourcemap.c: https://review.coreboot.org/#/c/26991/14/src/mainboard/asus/kfsn4-dre/resou… PS14, Line 229: // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, line over 80 characters https://review.coreboot.org/#/c/26991/14/src/mainboard/tyan/s2912_fam10/res… File src/mainboard/tyan/s2912_fam10/resourcemap.c: https://review.coreboot.org/#/c/26991/14/src/mainboard/tyan/s2912_fam10/res… PS14, Line 269: // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/agesa/family14… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/agesa/family14… PS14, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdht/h3gtopo.… PS14, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct/mct… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct/mct… PS14, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 710: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/lat… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/lat… PS14, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/lat… PS14, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/lat… PS14, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/lat… PS14, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/lat… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/lat… PS14, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/lat… PS14, Line 390: if (sb_config->AzaliaController == AZALIA_DISABLE) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/gfx.c@452 PS14, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/rs780.c@… PS14, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/sr5650/cmn.h@23 PS14, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 10:13:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek/mt8183: add pll and clock init support
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27031 ) Change subject: mediatek/mt8183: add pll and clock init support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28954/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74851/ : SUCCESS -- To view, visit https://review.coreboot.org/27031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Gerrit-Change-Number: 27031 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:43:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mediatek: Move mtcmos code to a common directory
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27029 ) Change subject: mediatek: Move mtcmos code to a common directory ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28953/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74850/ : SUCCESS -- To view, visit https://review.coreboot.org/27029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I92b138890424b4f4a68cdb00bf2326eef9cd87b7 Gerrit-Change-Number: 27029 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Kevin Paul Herbert <kph(a)meraki.net> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:39:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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