coreboot-gerrit June 2018

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Change in coreboot[master]: mb/google/poppy/variants/nami: Update DPTF table from version 1.5
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27086 ) Change subject: mb/google/poppy/variants/nami: Update DPTF table from version 1.5 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28944/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74841/ : SUCCESS -- To view, visit https://review.coreboot.org/27086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Gerrit-Change-Number: 27086 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 07:20:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Update DPTF table from version 1.5
by John Su (Code Review) 13 Jun '18

13 Jun '18

John Su has uploaded this change for review. ( https://review.coreboot.org/27086 Change subject: mb/google/poppy/variants/nami: Update DPTF table from version 1.5 ...................................................................... mb/google/poppy/variants/nami: Update DPTF table from version 1.5 Update dptf.asl and TCC parameters from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl 2 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27086/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 4d912d3..902179a 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -282,7 +282,7 @@ register "speed_shift_enable" = "1" - register "tcc_offset" = "10" # TCC of 90C + register "tcc_offset" = "3" # TCC of 90C register "psys_pmax" = "101" # PCH Trip Temperature in degree C diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index 05d5552..af40ab9 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -23,23 +23,23 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal_Sensor_Remote_CPU" -#define DPTF_TSR0_PASSIVE 81 +#define DPTF_TSR0_PASSIVE 75 #define DPTF_TSR0_CRITICAL 125 #define DPTF_TSR0_ACTIVE_AC0 50 #define DPTF_TSR0_ACTIVE_AC1 47 #define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 43 -#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal_Sensor_Remote_PMIC" -#define DPTF_TSR1_PASSIVE 78 +#define DPTF_TSR1_PASSIVE 75 #define DPTF_TSR1_CRITICAL 125 #define DPTF_TSR1_ACTIVE_AC0 50 #define DPTF_TSR1_ACTIVE_AC1 47 #define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 43 -#define DPTF_TSR1_ACTIVE_AC4 41 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -63,7 +63,7 @@ /* Control, Trip Point, Speed, NoiseLevel, Power */ Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, Package () {69, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {52, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {56, 0xFFFFFFFF, 5000, 145, 1450}, Package () {46, 0xFFFFFFFF, 4900, 115, 1150}, Package () {36, 0xFFFFFFFF, 3900, 90, 900} }) @@ -76,15 +76,15 @@ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 52, 46, 36, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 52, 46, 36, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 52, 46, 36, 0, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, 0, 0, 0 } }) -- To view, visit https://review.coreboot.org/27086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Gerrit-Change-Number: 27086 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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Change in coreboot[master]: src: Get rid of device_t
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27036 ) Change subject: src: Get rid of device_t ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28943/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74840/ : SUCCESS -- To view, visit https://review.coreboot.org/27036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Gerrit-Change-Number: 27036 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 07:01:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Get rid of device_t
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27036 ) Change subject: src: Get rid of device_t ...................................................................... Patch Set 5: (6 comments) https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 75: struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); line over 80 characters https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 97: struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); line over 80 characters https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 134: struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); line over 80 characters https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 318: struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); line over 80 characters https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 319: struct device *dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2)); line over 80 characters https://review.coreboot.org/#/c/27036/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 320: struct device *dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3)); line over 80 characters -- To view, visit https://review.coreboot.org/27036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Gerrit-Change-Number: 27036 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 06:55:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Use pci_devfn_t instead of device_t
by Elyes HAOUAS (Code Review) 13 Jun '18

13 Jun '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/27085 ) Change subject: src: Use pci_devfn_t instead of device_t ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/27085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I0ab62dd90a5ffdb504f5b9951877a32c345fc44d Gerrit-Change-Number: 27085 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Use pci_devfn_t instead of device_t
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27085 ) Change subject: src: Use pci_devfn_t instead of device_t ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28942/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74839/ : SUCCESS -- To view, visit https://review.coreboot.org/27085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ab62dd90a5ffdb504f5b9951877a32c345fc44d Gerrit-Change-Number: 27085 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 06:48:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Use pci_devfn_t instead of device_t
by Elyes HAOUAS (Code Review) 13 Jun '18

13 Jun '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27085 Change subject: src: Use pci_devfn_t instead of device_t ...................................................................... src: Use pci_devfn_t instead of device_t Change-Id: I0ab62dd90a5ffdb504f5b9951877a32c345fc44d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/debug.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/uart/uart.c 8 files changed, 66 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27085/1 diff --git a/src/lib/debug.c b/src/lib/debug.c index 6ae5985..80ee416 100644 --- a/src/lib/debug.c +++ b/src/lib/debug.c @@ -22,7 +22,11 @@ static inline void print_pci_devices(void) { - device_t dev; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev; +#else + struct device *dev; +#endif for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { u32 id; @@ -56,7 +60,11 @@ static inline void dump_pci_devices(void) { - device_t dev; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev; +#else + struct device *dev; +#endif for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { u32 id; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 02ab886..01a4928 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -164,7 +164,7 @@ soc_fill_fadt(fadt); } -unsigned long southbridge_write_acpi_tables(device_t device, +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { @@ -224,7 +224,7 @@ { } -void southbridge_inject_dsdt(device_t device) +void southbridge_inject_dsdt(struct device *device) { struct global_nvs_t *gnvs; @@ -407,7 +407,7 @@ { } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; int plen = 6; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 97ad176..e264348 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -31,7 +31,7 @@ static const void *microcode_patch; /* SoC override function */ -__weak void soc_core_init(device_t dev) +__weak void soc_core_init(struct device *dev) { /* no-op */ } @@ -41,7 +41,7 @@ /* no-op */ } -static void init_one_cpu(device_t dev) +static void init_one_cpu(struct device *dev) { soc_core_init(dev); intel_microcode_load_unlocked(microcode_patch); @@ -121,7 +121,7 @@ static void init_cpus(void *unused) { - device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); microcode_patch = intel_microcode_find(); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 4991db6..8651297 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -80,7 +80,11 @@ void heci_init(uintptr_t tempbar) { struct cse_device *cse = car_get_var_ptr(&g_cse); - device_t dev = PCH_DEV_CSE; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_CSE; +#else + struct device *dev = PCH_DEV_CSE; +#endif u8 pcireg; /* Assume it is already initialized, nothing else to do */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index b13408a..e7f81fc 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -34,7 +34,11 @@ */ void *fast_spi_get_bar(void) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uintptr_t bar; bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -51,7 +55,11 @@ */ void fast_spi_init(void) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t bios_cntl; bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); @@ -71,7 +79,11 @@ */ static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t bc_cntl; assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); @@ -253,7 +265,11 @@ */ void fast_spi_early_init(uintptr_t spi_base_address) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t pcireg; /* Assign Resources to SPI Controller */ @@ -285,7 +301,11 @@ /* Enable SPI Write Protect. */ void fast_spi_enable_wp(void) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t bios_cntl; bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 58b588e..d27f877 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -167,7 +167,11 @@ */ static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit) { - device_t dev = PCH_DEV_LPC; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_LPC; +#else + struct device *dev = PCH_DEV_LPC; +#endif uint8_t bc_cntl; assert(IS_POWER_OF_2(bios_cntl_bit)); @@ -210,7 +214,11 @@ */ void lpc_set_serirq_mode(enum serirq_mode mode) { - device_t dev = PCH_DEV_LPC; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_LPC; +#else + struct device *dev = PCH_DEV_LPC; +#endif uint8_t scnt; scnt = pci_read_config8(dev, LPC_SERIRQ_CTL); diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index cf50fdc..b8d798f 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -254,7 +254,11 @@ int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data, uint8_t *response) { - device_t dev = PCH_DEV_P2SB; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_P2SB; +#else + struct device *dev = PCH_DEV_P2SB; +#endif uint32_t sbi_data; uint16_t sbi_status; uint16_t sbi_rid; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index cdbe56b..b84a7ec 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -59,7 +59,11 @@ bool uart_debug_controller_is_initialized(void) { - device_t dev; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev; +#else + struct device *dev; +#endif uintptr_t base; dev = pch_uart_get_debug_controller(); -- To view, visit https://review.coreboot.org/27085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0ab62dd90a5ffdb504f5b9951877a32c345fc44d Gerrit-Change-Number: 27085 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mediatek/mt8183: Add watchdog timer support
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27026 ) Change subject: mediatek/mt8183: Add watchdog timer support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28941/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74838/ : SUCCESS -- To view, visit https://review.coreboot.org/27026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4 Gerrit-Change-Number: 27026 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 06:40:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek: Share watchdog timer code among similar SOCs
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27024 ) Change subject: mediatek: Share watchdog timer code among similar SOCs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28939/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74836/ : SUCCESS -- To view, visit https://review.coreboot.org/27024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958 Gerrit-Change-Number: 27024 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 06:38:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek: Move watchdog timer code to a common directory
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27025 ) Change subject: mediatek: Move watchdog timer code to a common directory ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28940/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74837/ : SUCCESS -- To view, visit https://review.coreboot.org/27025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbeb04f775c3c0fdc18dd198df8591f5c4b6ddce Gerrit-Change-Number: 27025 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 06:36:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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