coreboot-gerrit June 2018

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Change in coreboot[master]: src: Get rid of unneeded whitespace
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

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Change in coreboot[master]: mediatek/mt8183: Add mtcmos init support
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27030 ) Change subject: mediatek/mt8183: Add mtcmos init support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28952/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74849/ : SUCCESS -- To view, visit https://review.coreboot.org/27030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 Gerrit-Change-Number: 27030 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:35:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek: Share mtcmos code among similar SOCs
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27028 ) Change subject: mediatek: Share mtcmos code among similar SOCs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28951/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74848/ : SUCCESS -- To view, visit https://review.coreboot.org/27028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774 Gerrit-Change-Number: 27028 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:31:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27088 ) Change subject: mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28950/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74847/ : SUCCESS -- To view, visit https://review.coreboot.org/27088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c Gerrit-Change-Number: 27088 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:27:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Update DPTF table from version 1.5
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27086 ) Change subject: mb/google/poppy/variants/nami: Update DPTF table from version 1.5 ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28949/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74846/ : SUCCESS -- To view, visit https://review.coreboot.org/27086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Gerrit-Change-Number: 27086 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:23:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation/Intel: Add common code design document
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27087 ) Change subject: Documentation/Intel: Add common code design document ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28948/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74845/ : SUCCESS -- To view, visit https://review.coreboot.org/27087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Gerrit-Change-Number: 27087 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 09:19:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV
by John Su (Code Review) 13 Jun '18

13 Jun '18

John Su has uploaded this change for review. ( https://review.coreboot.org/27088 Change subject: mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV ...................................................................... mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem. BUG=b:109941652 TEST=The thermal team verify OK Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27088/1 diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index af40ab9..c1a13d5 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -98,7 +98,7 @@ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 1, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 }, #endif }) -- To view, visit https://review.coreboot.org/27088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c Gerrit-Change-Number: 27088 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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Change in coreboot[master]: Documentation/Intel: Add common code design document
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27087 ) Change subject: Documentation/Intel: Add common code design document ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/28947/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74844/ : SUCCESS -- To view, visit https://review.coreboot.org/27087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Gerrit-Change-Number: 27087 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 08:56:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation/Intel: Add common code design document
by Maulik V Vaghela (Code Review) 13 Jun '18

13 Jun '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27087 Change subject: Documentation/Intel: Add common code design document ...................................................................... Documentation/Intel: Add common code design document Add common code design document support Intel SoCs such as Skylake, Cannonlake and Apollolake onwards. Documented items: *Introduction *Design Principle *Common code development and status *Common code structure *Benifits Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- A Documentation/Intel/code_development_model/Code_development_model.md A Documentation/Intel/code_development_model/coreboot_common_code_design.png 2 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/27087/1 diff --git a/Documentation/Intel/code_development_model/Code_development_model.md b/Documentation/Intel/code_development_model/Code_development_model.md new file mode 100644 index 0000000..9e03404 --- /dev/null +++ b/Documentation/Intel/code_development_model/Code_development_model.md @@ -0,0 +1,93 @@ +# Intel common code development strategy + +## Introduction + +This document captures the development strategy for Intel SOC code development +of coreboot. As Intel keeps advancing hardware development and as new generation +SoC is developed, we also need to add support for these SOCs into coreboot. + +We add this support inside soc/intel/<soc name> folder. This folder contains all +the files which are related to particular SoC. + +There might be still common code lying across some SoCs but this document +captures our efforts on putting maximum code as a common code across all the +SoCs and what can't be put into common code due to vulnerability to change in +future. + +## Design principal + +Any Intel coreboot projects can be split into 3 parts: +1. SoC = It contains all the IP/component initialization code +2. Mainboard = OxM boards, build based on underlying SoC support +3. FSP = Intel firmware support package to abstract all restricted SoC registers +from open source world. + +Historically, we used to copy "X-1" generation SoC code into "X" new SoC while +adding support for new SoC at open source. This results in having same +initialization code in both projects. This method increases redundant code +across multiple SoCs and also it increases overhead for reviewers and +maintainers also. + +To solve this issue, we started following converged IP model. Intel Silicon team +uses same IP/controller across various Intel SoCs. For example, LPSS based UART +controller is same across all SoC products. Thus "converged IP model" was +propsed as firmware development model to create common IP library across +multiple SoC products and creating BIOS/firmware for future SoC will be much +simpler by just using those APIs based on certain configurations. + +## Common Code Development and Status + +Intel's proposed "converged IP model" is also called as common code phase 1.0, +and it has reduced number of lines in single SoC folder by over 50%. + +We continue to analyze code which can still be moved to common and try to reduce +footprint of the code lying in each SoC folder. With current Intel SoC +development model, PCH is emerged as a separate component for big core SoCs. +Intel hardware design started following model where same PCH is used across +multiple SoCs, which gives us an opportunity to make code more common across +SoCs which uses same PCH. As part of this idea, common code phase 1.1 has +emerged and we'll try to create PCH binding for SoCs and thus further reducing +footprint of SoC code. + +Common code phase 1.1 will make code more modular for big core SoCs but there +is still some scope to make code flow common across small core and big core +SoCs. We will take it up as a part of common code phase 2.0 and make code flow +common across small core and big core SoCs which will help us to reduce the +footprint of code as well as have a unified code flow for all Intel SoCs. + +Here's a table which summarizes common code phase and status: +|-----------------------------------------------------------------------------| +| Common code | summary | status | +| phase | | | +|-----------------------------------------------------------------------------| +| 1.0 |follow "converged IP model" as described | Patches in | +| |above and create common IP code which can be | Review | +| |used across multiple SoCs | | +|-----------------------------------------------------------------------------| +| 1.1 |Create PCH binding for big core SoCs. SoCs |In development| +| |having same PCH can use common code. |Base patch | +| | |merged | +|-----------------------------------------------------------------------------| +| 2.0 |Use common stage files (bootblock, romstage) |In development| +| |across small core and big core SoCs. This | | +| |will unify flow for all Intel SoCs. | | +|-----------------------------------------------------------------------------| + +## Common code structure + +Code design after common code in coreboot will look like as follow: + +![alt text][coreboot_common_code_design] +[coreboot_common_code_design]: coreboot_common_code_design.png "coreboot common code structure" + +There will be still some files left in each SOC folder and we may copy it across +SOC as a base but these files are vulnerable to change as development continues. + +## Benefits + +1. coreboot will have less redundant code which is spread across multiple SOC +as of now. +2. Design will be easy to understand by community since code flow will be same +for all the SoCs. +3. Since we are aligning software code design with hardware philosophy, it'll +be easier to map why each change was done in code/SOC. diff --git a/Documentation/Intel/code_development_model/coreboot_common_code_design.png b/Documentation/Intel/code_development_model/coreboot_common_code_design.png new file mode 100644 index 0000000..b5370ef --- /dev/null +++ b/Documentation/Intel/code_development_model/coreboot_common_code_design.png Binary files differ -- To view, visit https://review.coreboot.org/27087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Gerrit-Change-Number: 27087 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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Change in coreboot[master]: src: Get rid of unneeded whitespace
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Get rid of unneeded whitespace ...................................................................... Patch Set 13: (21 comments) https://review.coreboot.org/#/c/26991/13/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/13/src/include/bootstate.h@127 PS13, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/13/src/mainboard/amd/bimini_fam10/rom… File src/mainboard/amd/bimini_fam10/romstage.c: https://review.coreboot.org/#/c/26991/13/src/mainboard/amd/bimini_fam10/rom… PS13, Line 83: inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/mainboard/amd/tilapia_fam10/ma… File src/mainboard/amd/tilapia_fam10/mainboard.c: https://review.coreboot.org/#/c/26991/13/src/mainboard/amd/tilapia_fam10/ma… PS13, Line 153: /* When the gpio40 is configured as GPIO, this will represent the output value*/ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/mainboard/amd/tilapia_fam10/ma… PS13, Line 165: /* When the gpio40 is configured as GPIO, this will represent the output value*/ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/mainboard/asus/kfsn4-dre/resou… File src/mainboard/asus/kfsn4-dre/resourcemap.c: https://review.coreboot.org/#/c/26991/13/src/mainboard/asus/kfsn4-dre/resou… PS13, Line 229: // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, line over 80 characters https://review.coreboot.org/#/c/26991/13/src/mainboard/tyan/s2912_fam10/res… File src/mainboard/tyan/s2912_fam10/resourcemap.c: https://review.coreboot.org/#/c/26991/13/src/mainboard/tyan/s2912_fam10/res… PS13, Line 269: // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/agesa/family14… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/agesa/family14… PS13, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdht/h3gtopo.… PS13, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct/mct… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct/mct… PS13, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct_ddr… PS13, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct_ddr… PS13, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/13/src/northbridge/amd/amdmct/mct_ddr… PS13, Line 710: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb800/lat… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb800/lat… PS13, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb800/lat… PS13, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb800/lat… PS13, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb800/lat… PS13, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb900/lat… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb900/lat… PS13, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/cimx/sb900/lat… PS13, Line 390: if (sb_config->AzaliaController == AZALIA_DISABLE) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/rs780/gfx.c@452 PS13, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/rs780/rs780.c@… PS13, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/13/src/southbridge/amd/sr5650/cmn.h@23 PS13, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Jun 2018 08:32:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit June 2018