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Change in coreboot[master]: src/cpu: Remove unneeded headers
by Elyes HAOUAS (Code Review)
31 May '18
31 May '18
Elyes HAOUAS has uploaded this change for review. (
https://review.coreboot.org/26732
Change subject: src/cpu: Remove unneeded headers ...................................................................... src/cpu: Remove unneeded headers Change-Id: I8fb03ada29b37f96fb02122462dfb8ec7faa9d31 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/bootblock.c M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_69x/model_69x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6dx/model_6dx_init.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/tsc/delay_tsc.c 10 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/26732/1 diff --git a/src/cpu/intel/fsp_model_206ax/bootblock.c b/src/cpu/intel/fsp_model_206ax/bootblock.c index ed68883..45c92bf 100644 --- a/src/cpu/intel/fsp_model_206ax/bootblock.c +++ b/src/cpu/intel/fsp_model_206ax/bootblock.c @@ -16,8 +16,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/io.h> #include <cpu/intel/microcode/microcode.c> diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 9eab9c7..773a693 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 4fd51d3..cb4b8ed 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -22,7 +22,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> #include <cpu/intel/l2_cache.h> static void model_67x_init(struct device *cpu) diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 17c9eb7..f54731b 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -20,7 +20,6 @@ #include <string.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 785c480..3d1a6d9 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -16,7 +16,6 @@ #include <string.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index ce70539..9e2bc4e 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -20,7 +20,6 @@ #include <string.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 6097c33..59f6dbe 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -16,7 +16,6 @@ #include <string.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 05eaeb3..885d4d7 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -42,7 +42,6 @@ #include <console/console.h> #include <string.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/intel/l2_cache.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index ca0ff94..8cd3092 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -13,8 +13,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> void do_lapic_init(void) { diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index ec2f1d7..04f709f 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -14,7 +14,6 @@ #include <arch/early_variables.h> #include <console/console.h> #include <arch/io.h> -#include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <smp/spinlock.h> #include <delay.h> -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8fb03ada29b37f96fb02122462dfb8ec7faa9d31 Gerrit-Change-Number: 26732 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
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Change in coreboot[master]: soc/intel/common: Allow RX level/edge configuartion for IOAPIC IRQ mode
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26730
) Change subject: soc/intel/common: Allow RX level/edge configuartion for IOAPIC IRQ mode ...................................................................... Patch Set 4: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/73802/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Gerrit-Change-Number: 26730 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 11:38:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: soc/intel/common/block: Move tco common functions into block/smbus
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26166
) Change subject: soc/intel/common/block: Move tco common functions into block/smbus ...................................................................... Patch Set 28: Verified-1 Build Unstable
https://qa.coreboot.org/job/coreboot-gerrit/73800/
: UNSTABLE
https://qa.coreboot.org/job/coreboot-checkpatch/27917/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Gerrit-Change-Number: 26166 Gerrit-PatchSet: 28 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 11:33:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/common/block: Move cse common functions into block/cse
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26133
) Change subject: soc/intel/common/block: Move cse common functions into block/cse ...................................................................... Patch Set 31: Verified-1 Build Unstable
https://qa.coreboot.org/job/coreboot-gerrit/73798/
: UNSTABLE
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: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Gerrit-Change-Number: 26133 Gerrit-PatchSet: 31 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 11:31:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/common/block: Move common uart function to block/uart
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26164
) Change subject: soc/intel/common/block: Move common uart function to block/uart ...................................................................... Patch Set 32: Verified-1 Build Unstable
https://qa.coreboot.org/job/coreboot-gerrit/73799/
: UNSTABLE
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Gerrit-Change-Number: 26164 Gerrit-PatchSet: 32 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 11:29:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into block/s...
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26138
) Change subject: soc/intel/common/block: Move smihandler common functions into block/smihandler ...................................................................... Patch Set 30: Verified-1 Build Unstable
https://qa.coreboot.org/job/coreboot-gerrit/73797/
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Change in coreboot[master]: soc/intel/common/block: Move i2c common functions into block/i2c
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26056
) Change subject: soc/intel/common/block: Move i2c common functions into block/i2c ...................................................................... Patch Set 33: Build Successful
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Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
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) Change subject: soc/intel/common/block: Move p2sb common functions into block/p2sb ...................................................................... Patch Set 35: Verified-1 Build Unstable
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Change in coreboot[master]: soc/intel/common/pch: Add pch lockdown code
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
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) Change subject: soc/intel/common/pch: Add pch lockdown code ...................................................................... Patch Set 61: Build Successful
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Change in coreboot[master]: soc/intel/common: Allow RX level/edge configuartion for IOAPIC IRQ mode
by build bot (Jenkins) (Code Review)
31 May '18
31 May '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/26730
) Change subject: soc/intel/common: Allow RX level/edge configuartion for IOAPIC IRQ mode ...................................................................... Patch Set 3: Verified+1 Build Failed
https://qa.coreboot.org/job/coreboot-checkpatch/27919/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Gerrit-Change-Number: 26730 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 11:17:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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