coreboot-gerrit May 2018

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Change in coreboot[master]: soc/intel/common/block: Move i2c common functions into block/i2c
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26056 ) Change subject: soc/intel/common/block: Move i2c common functions into block/i2c ...................................................................... Patch Set 32: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73779/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27896/ : SUCCESS -- To view, visit https://review.coreboot.org/26056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Gerrit-Change-Number: 26056 Gerrit-PatchSet: 32 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 10:26:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26731 ) Change subject: mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/26731/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/26731/1/src/mainboard/google/octopus/varian… PS1, Line 196: PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP, LEVEL),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/26731/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/26731/1/src/mainboard/google/octopus/varian… PS1, Line 194: PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP, LEVEL),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters -- To view, visit https://review.coreboot.org/26731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85dab Gerrit-Change-Number: 26731 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 10:26:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode
by Aamir Bohra (Code Review) 31 May '18

31 May '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/26731 Change subject: mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode ...................................................................... mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode Update GPIO pad configuartion in IOAPIC invert mode to include RX level/edge Configuration. Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85dab Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bip/gpio.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 6 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/26731/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index f839850..bf9bd7b 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -193,7 +193,7 @@ // TODO Need to set HIZCRx1 PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */ - PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP, LEVEL),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */ diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index 17fc105..231f942 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -191,7 +191,7 @@ // TODO Need to set HIZCRx1 PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */ - PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP, LEVEL),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */ diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 3cd765b..110f257 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -263,7 +263,7 @@ PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ /* Headset interrupt */ - PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP, LEVEL), /* SIO_SPI_1_RXD */ PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ /* SIO_SPI_2 -- unused */ @@ -286,31 +286,31 @@ PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), - PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP, LEVEL), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */ PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP, LEVEL), /* PEN_INT_ODL */ PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */ - PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP, LEVEL), /* Trackpad IRQ */ PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ - PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP, LEVEL), /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP, LEVEL), /* Touch IRQ */ PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE), /* EC wake */ PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */ PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */ PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ - PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP, LEVEL), /* KB IRQ */ PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ - PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP, LEVEL), /* PMIC IRQ */ PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ @@ -358,7 +358,7 @@ /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */ /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; @@ -373,7 +373,7 @@ /* GPIO settings before entering sleep. */ static const struct pad_config sleep_gpio_table[] = { PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */ }; const struct pad_config * __weak diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index e89e5b5..f97b66a 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -263,7 +263,7 @@ PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ /* Headset interrupt */ - PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP, LEVEL), /* SIO_SPI_1_RXD */ PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ /* SIO_SPI_2 -- unused */ @@ -286,31 +286,31 @@ PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), - PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP, LEVEL), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */ PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP, LEVEL), /* PEN_INT_ODL */ PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */ - PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP, LEVEL), /* Trackpad IRQ */ PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ - PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP, LEVEL), /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP, LEVEL), /* Touch IRQ */ PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE), /* EC wake */ PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */ PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */ PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ - PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP, LEVEL), /* KB IRQ */ PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ - PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP, LEVEL), /* PMIC IRQ */ PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ @@ -358,7 +358,7 @@ /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ - PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */ /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; @@ -372,14 +372,14 @@ /* Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */ }; /* GPIO settings before entering S5, which are same as default_sleep_gpio_table * but also turn off EN_PP3300_DX_LTE_SOC. */ static const struct pad_config s5_sleep_gpio_table[] = { PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */ PAD_CFG_GPO(GPIO_78, 0, DEEP), /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */ }; diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index fa9d0e9..955126a 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -50,7 +50,7 @@ /* A19 : ISH_GP_1 */ PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), /* A20 : aduio codec irq */ - PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP), + PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP, LEVEL), /* A21 : ISH_GP_3 */ PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), /* A22 : ISH_GP_4 */ diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 7ff68a4..c763eca 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -274,7 +274,7 @@ static const struct pad_config sleep_gpio_table[] = { #if 0 PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */ #endif }; -- To view, visit https://review.coreboot.org/26731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85dab Gerrit-Change-Number: 26731 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Allow RX level/Edge configuartion to be set for IOA...
by Aamir Bohra (Code Review) 31 May '18

31 May '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/26730 Change subject: soc/intel/common: Allow RX level/Edge configuartion to be set for IOAPIC IRQ mode ...................................................................... soc/intel/common: Allow RX level/Edge configuartion to be set for IOAPIC IRQ mode GPIO configuration in IOAPIC mode is not limited to only LEVEL trigger mode. This implementation allows level/edge/ either/none trigger configuration to be set for a GPIO in IOAPIC mode with RX Invert configuration. Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26730/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 244c680..13d08e7 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -278,8 +278,8 @@ * on its own end. One just needs to pass an active high message into the * ITSS. */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ - PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_APIC(pad, pull, rst, trig, INVERT) #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) -- To view, visit https://review.coreboot.org/26730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Gerrit-Change-Number: 26730 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: soc/intel/common/pch: Add pch lockdown code
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25688 ) Change subject: soc/intel/common/pch: Add pch lockdown code ...................................................................... Patch Set 60: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73777/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27894/ : SUCCESS -- To view, visit https://review.coreboot.org/25688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Gerrit-Change-Number: 25688 Gerrit-PatchSet: 60 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 10:24:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block: Move gspi common functions into block/gspi
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26048 ) Change subject: soc/intel/common/block: Move gspi common functions into block/gspi ...................................................................... Patch Set 34: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73778/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27895/ : SUCCESS -- To view, visit https://review.coreboot.org/26048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Gerrit-Change-Number: 26048 Gerrit-PatchSet: 34 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 31 May 2018 10:22:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/pch: Make infrastructure ready for pch common code
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26348 ) Change subject: soc/intel/common/pch: Make infrastructure ready for pch common code ...................................................................... Patch Set 14: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73776/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27893/ : SUCCESS -- To view, visit https://review.coreboot.org/26348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b Gerrit-Change-Number: 26348 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 10:18:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block: Add common chip config block
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26189 ) Change subject: soc/intel/common/block: Add common chip config block ...................................................................... Patch Set 23: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73775/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27892/ : SUCCESS -- To view, visit https://review.coreboot.org/26189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Gerrit-Change-Number: 26189 Gerrit-PatchSet: 23 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Thu, 31 May 2018 10:17:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26349 ) Change subject: soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL ...................................................................... Patch Set 15: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73774/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27891/ : SUCCESS -- To view, visit https://review.coreboot.org/26349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Gerrit-Change-Number: 26349 Gerrit-PatchSet: 15 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 10:14:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: intel/common/pch/i2c: Move i2c file to common PCH
by Maulik V Vaghela (Code Review) 31 May '18

31 May '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26729 Change subject: intel/common/pch/i2c: Move i2c file to common PCH ...................................................................... intel/common/pch/i2c: Move i2c file to common PCH i2c.c file is common across soc which uses common PCH base code. Move i2c related files from cannonlake and skylake to PCH base code. BUG=none BRANCH=none TEST= Check if code compiles with the patch and boot with SKL/CNL boards Change-Id: I333ca3f3e96505993c81fd3113c68d1f92b8f1b8 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/common/pch/Kconfig A src/soc/intel/common/pch/i2c/Kconfig A src/soc/intel/common/pch/i2c/Makefile.inc R src/soc/intel/common/pch/i2c/i2c.c M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/i2c.c 7 files changed, 10 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/26729/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 4cce5c3..f070723 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -14,7 +14,6 @@ bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c -bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += lpc.c @@ -23,7 +22,6 @@ romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c romstage-y += gpio.c -romstage-y += i2c.c romstage-y += lpc.c romstage-y += memmap.c romstage-y += pmutil.c @@ -38,7 +36,6 @@ ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += gpio.c -ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += memmap.c @@ -64,7 +61,6 @@ postcar-y += pmutil.c postcar-$(CONFIG_UART_DEBUG) += uart.c -verstage-y += i2c.c verstage-y += pmutil.c verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 9014647..ff58524 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -45,4 +45,5 @@ select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN select SOC_INTEL_COMMON_PCH_GSPI + select SOC_INTEL_COMMON_PCH_I2C endif diff --git a/src/soc/intel/common/pch/i2c/Kconfig b/src/soc/intel/common/pch/i2c/Kconfig new file mode 100644 index 0000000..1809cb6 --- /dev/null +++ b/src/soc/intel/common/pch/i2c/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_PCH_I2C + bool + default n + help + This option allows to have i2c configuration for supported PCH. diff --git a/src/soc/intel/common/pch/i2c/Makefile.inc b/src/soc/intel/common/pch/i2c/Makefile.inc new file mode 100644 index 0000000..04328b7 --- /dev/null +++ b/src/soc/intel/common/pch/i2c/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c +verstage-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c +romstage-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_I2C) += i2c.c diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/common/pch/i2c/i2c.c similarity index 100% rename from src/soc/intel/cannonlake/i2c.c rename to src/soc/intel/common/pch/i2c/i2c.c diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 8f673c3..03b293a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -11,7 +11,6 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c -bootblock-y += i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c @@ -22,12 +21,10 @@ bootblock-$(CONFIG_UART_DEBUG) += uart.c verstage-y += pmutil.c -verstage-y += i2c.c verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c romstage-y += gpio.c -romstage-y += i2c.c romstage-y += memmap.c romstage-y += me.c romstage-y += pei_data.c @@ -44,7 +41,6 @@ ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += gpio.c -ramstage-y += i2c.c ramstage-y += graphics.c ramstage-y += irq.c ramstage-y += lockdown.c diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c deleted file mode 100644 index 9fd9bf3..0000000 --- a/src/soc/intel/skylake/i2c.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <intelblocks/chip.h> -#include <drivers/i2c/designware/dw_i2c.h> -#include <soc/pci_devs.h> - -int dw_i2c_soc_devfn_to_bus(unsigned int devfn) -{ - switch (devfn) { - case PCH_DEVFN_I2C0: - return 0; - case PCH_DEVFN_I2C1: - return 1; - case PCH_DEVFN_I2C2: - return 2; - case PCH_DEVFN_I2C3: - return 3; - case PCH_DEVFN_I2C4: - return 4; - case PCH_DEVFN_I2C5: - return 5; - } - return -1; -} - -int dw_i2c_soc_bus_to_devfn(unsigned int bus) -{ - switch (bus) { - case 0: - return PCH_DEVFN_I2C0; - case 1: - return PCH_DEVFN_I2C1; - case 2: - return PCH_DEVFN_I2C2; - case 3: - return PCH_DEVFN_I2C3; - case 4: - return PCH_DEVFN_I2C4; - case 5: - return PCH_DEVFN_I2C5; - } - return -1; -} -- To view, visit https://review.coreboot.org/26729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I333ca3f3e96505993c81fd3113c68d1f92b8f1b8 Gerrit-Change-Number: 26729 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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coreboot-gerrit May 2018