coreboot-gerrit May 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/pch: Make infrastructure ready for pch common code
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26348 ) Change subject: soc/intel/common/pch: Make infrastructure ready for pch common code ...................................................................... Patch Set 16: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73817/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27931/ : SUCCESS -- To view, visit https://review.coreboot.org/26348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b Gerrit-Change-Number: 26348 Gerrit-PatchSet: 16 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 31 May 2018 14:40:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block: Move gspi common functions into block/gspi
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26048 ) Change subject: soc/intel/common/block: Move gspi common functions into block/gspi ...................................................................... Patch Set 36: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73819/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27933/ : SUCCESS -- To view, visit https://review.coreboot.org/26048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Gerrit-Change-Number: 26048 Gerrit-PatchSet: 36 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 31 May 2018 14:39:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block: Move i2c common functions into block/i2c
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26056 ) Change subject: soc/intel/common/block: Move i2c common functions into block/i2c ...................................................................... Patch Set 34: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73818/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27932/ : SUCCESS -- To view, visit https://review.coreboot.org/26056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Gerrit-Change-Number: 26056 Gerrit-PatchSet: 34 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 14:35:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block: Add common chip config block
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26189 ) Change subject: soc/intel/common/block: Add common chip config block ...................................................................... Patch Set 25: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73816/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27930/ : SUCCESS -- To view, visit https://review.coreboot.org/26189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Gerrit-Change-Number: 26189 Gerrit-PatchSet: 25 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Thu, 31 May 2018 14:31:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/lib: Remove unneeded 'console.h' include
by Elyes HAOUAS (Code Review) 31 May '18

31 May '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26735 Change subject: src/lib: Remove unneeded 'console.h' include ...................................................................... src/lib: Remove unneeded 'console.h' include Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/bootblock.c M src/lib/cbmem_console.c M src/lib/timer.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26735/1 diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index d74bebf..2944f9f 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -17,7 +17,6 @@ #include <arch/exception.h> #include <bootblock_common.h> #include <compiler.h> -#include <console/console.h> #include <delay.h> #include <pc80/mc146818rtc.h> #include <program_loading.h> diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index d971670..3b352b2 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -14,7 +14,6 @@ */ #include <compiler.h> -#include <console/console.h> #include <console/cbmem_console.h> #include <console/uart.h> #include <cbmem.h> diff --git a/src/lib/timer.c b/src/lib/timer.c index 625bfc0..2cb76dd 100644 --- a/src/lib/timer.c +++ b/src/lib/timer.c @@ -14,7 +14,6 @@ */ #include <compiler.h> -#include <console/console.h> #include <timer.h> #include <delay.h> #include <thread.h> -- To view, visit https://review.coreboot.org/26735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Gerrit-Change-Number: 26735 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: northbridge/intel: Remove unneeded includes
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26734 ) Change subject: northbridge/intel: Remove unneeded includes ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73815/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27929/ : SUCCESS -- To view, visit https://review.coreboot.org/26734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Gerrit-Change-Number: 26734 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 14:25:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: northbridge/intel: Remove unneeded includes
by Elyes HAOUAS (Code Review) 31 May '18

31 May '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26734 to look at the new patch set (#2). Change subject: northbridge/intel: Remove unneeded includes ...................................................................... northbridge/intel: Remove unneeded includes Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/x4x/gma.c 15 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/26734/2 -- To view, visit https://review.coreboot.org/26734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Gerrit-Change-Number: 26734 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: northbridge/intel: Remove unneeded includes
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26734 ) Change subject: northbridge/intel: Remove unneeded includes ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/73814/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/27928/ : SUCCESS -- To view, visit https://review.coreboot.org/26734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Gerrit-Change-Number: 26734 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 14:15:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: northbridge/intel: Remove unneeded includes
by Elyes HAOUAS (Code Review) 31 May '18

31 May '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26734 Change subject: northbridge/intel: Remove unneeded includes ...................................................................... northbridge/intel: Remove unneeded includes Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/x4x/gma.c 16 files changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/26734/1 diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index af652ee..27153f8 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <delay.h> #include <cpu/intel/fsp_model_406dx/model_406dx.h> -#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 1016c8b..24969d4 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <delay.h> #include <cpu/intel/fsp_model_206ax/model_206ax.h> -#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 237071c..f0171e6 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -22,8 +22,6 @@ #include <device/pci_ids.h> #include <string.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <commonlib/helpers.h> #include <cbmem.h> #include <southbridge/intel/i82801ix/nvs.h> diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 613e982..f61a478 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <delay.h> #include <cpu/intel/haswell/haswell.h> -#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 483d5d3..6719961 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <device/device.h> diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 6b8b98e..aeff69a 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -22,8 +22,6 @@ #include <device/pci_ids.h> #include <string.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/intel_bios.h> diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 0303e92..6fc61c3 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -22,7 +22,6 @@ #include <delay.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 6a27b57..ca7fddb 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -40,7 +40,6 @@ #include "raminit.h" #include "chip.h" #include <timestamp.h> -#include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <mrc_cache.h> diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index ec332e6..8cf4d22 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -23,8 +23,6 @@ #include <device/pci_ids.h> #include <string.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <drivers/intel/gma/i915_reg.h> #include "chip.h" diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 1f03820..356c730 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -17,7 +17,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <delay.h> #include <halt.h> #include <lib.h> diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 201498a..73546ce 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -22,8 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <drivers/intel/gma/libgfxinit.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index eb8ce26..8c2aaf3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -21,7 +21,6 @@ #include <delay.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5f6753f..b82075e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -26,7 +26,6 @@ #include <device/pci_def.h> #include <delay.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 19dea2f..88d8bd6 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <console/usb.h> -#include <cpu/x86/msr.h> #include <delay.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 99c107e..9fa6c7b 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <console/usb.h> -#include <cpu/x86/msr.h> #include <delay.h> #include "raminit_native.h" #include "raminit_common.h" diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 8ce1a5d..6c6f3a2 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -23,8 +23,6 @@ #include <device/pci_ids.h> #include <string.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <commonlib/helpers.h> #include <cbmem.h> -- To view, visit https://review.coreboot.org/26734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Gerrit-Change-Number: 26734 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 33: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73813/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 33 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 31 May 2018 13:53:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit May 2018