coreboot-gerrit May 2018

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Change in coreboot[master]: soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26349 ) Change subject: soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL ...................................................................... Patch Set 18: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/73825/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/27939/ : SUCCESS -- To view, visit https://review.coreboot.org/26349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Gerrit-Change-Number: 26349 Gerrit-PatchSet: 18 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 31 May 2018 16:28:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/pch: Make infrastructure ready for pch common code
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26348 ) Change subject: soc/intel/common/pch: Make infrastructure ready for pch common code ...................................................................... Patch Set 17: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/73826/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/27940/ : SUCCESS -- To view, visit https://review.coreboot.org/26348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b Gerrit-Change-Number: 26348 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 31 May 2018 16:25:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: configure the FPMCU interface
by Martin Roth (Code Review) 31 May '18

31 May '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/26684 ) Change subject: mb/google/poppy/variants/nocturne: configure the FPMCU interface ...................................................................... mb/google/poppy/variants/nocturne: configure the FPMCU interface The FPMCU is using the standard cros-ec-spi interface on GSPI1. Configure the GPIOs controlling the MCU too. We need to be able to wake from S3 on the MCU interrupt, re-configure GPE0 DW0 to point to GPP_C bank. BRANCH=poppy BUG=b:79666174 TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version', verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup' then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs with the flash_fp_mcu script. Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 Signed-off-by: Vincent Palatin <vpalatin(a)chromium.org> Reviewed-on: https://review.coreboot.org/26684 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/gpio.c 2 files changed, 25 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 621bbe4..91e8b46 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -11,7 +11,7 @@ # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -326,7 +326,23 @@ device spi 0 on end end end # GSPI #0 - device pci 1e.3 on end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)" + register "wake" = "GPE0_DW0_09" # GPP_C9 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "0" + register "reset_off_delay_ms" = "0" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "enable_delay_ms" = "0" + register "enable_off_delay_ms" = "0" + register "has_power_resource" = "1" + device spi 0 on end + end + end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index bd38a20..be76b64 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -39,8 +39,8 @@ PAD_CFG_NC(GPP_A10), /* A11 : PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A11, 0, DEEP), - /* A12 : FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_A12, NONE, DEEP), + /* A12 : ISH_GP6 */ + PAD_CFG_NC(GPP_A12), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -108,7 +108,7 @@ /* B21 : GSPI1_MISO ==> PCH_FPMCU_SPI_MISO_R */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* B23 : SM1ALERT# ==> PCHHOT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), @@ -129,13 +129,13 @@ /* C7 : SM1DATA ==> NC */ PAD_CFG_NC(GPP_C7), /* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */ - PAD_CFG_NC(GPP_C8), + PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> FPMCU_INT */ - PAD_CFG_NC(GPP_C9), + PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ - PAD_CFG_NC(GPP_C10), + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_NC(GPP_C11), + PAD_CFG_GPI_APIC_INVERT(GPP_C11, NONE, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ -- To view, visit https://review.coreboot.org/26684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 Gerrit-Change-Number: 26684 Gerrit-PatchSet: 3 Gerrit-Owner: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/sconfig: Get rid of bus pointer in device structure
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26736 ) Change subject: util/sconfig: Get rid of bus pointer in device structure ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73824/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27938/ : SUCCESS -- To view, visit https://review.coreboot.org/26736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844 Gerrit-Change-Number: 26736 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 15:09:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/lib: Remove unneeded 'console.h' include
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26735 ) Change subject: src/lib: Remove unneeded 'console.h' include ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73823/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27937/ : SUCCESS -- To view, visit https://review.coreboot.org/26735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Gerrit-Change-Number: 26735 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 15:08:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Enable RT5682 headset codec for BIP board
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26211 ) Change subject: mb/google/octopus: Enable RT5682 headset codec for BIP board ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73822/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27936/ : SUCCESS -- To view, visit https://review.coreboot.org/26211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee91518c03a0e9e6ed52bc54a60fc607730a0b7d Gerrit-Change-Number: 26211 Gerrit-PatchSet: 10 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 15:05:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/sconfig: Get rid of bus pointer in device structure
by Furquan Shaikh (Code Review) 31 May '18

31 May '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/26736 Change subject: util/sconfig: Get rid of bus pointer in device structure ...................................................................... util/sconfig: Get rid of bus pointer in device structure The only reason bus pointer existed in device structure in sconfig was to allow a node to point to the parent which could be a chip and bus which is the true parent in device tree hierarchy. Now that chip is no longer a device, there is no need for separate bus and parent pointers. This change gets rid of the redundant bus pointer in struct device in sconfig. BUG=b:80081934 TEST=Verified that static.c generated for all boards built by abuild is same with and without this change. Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.y 4 files changed, 20 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/26736/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 373eb87..41e850c 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -50,7 +50,6 @@ .path = " .type = DEVICE_PATH_ROOT ", .ops = "&default_dev_ops_root", .parent = &root, - .bus = &root, .enabled = 1 }; @@ -107,13 +106,12 @@ return c; } -static struct device *new_dev(struct device *parent, struct device *bus) +static struct device *new_dev(struct device *parent) { struct device *dev = malloc(sizeof(struct device)); memset(dev, 0, sizeof(struct device)); dev->id = ++count; dev->parent = parent; - dev->bus = bus; dev->subsystem_vendor = -1; dev->subsystem_device = -1; head->next = dev; @@ -123,7 +121,7 @@ static int device_match(struct device *a, struct device *b) { - if ((a->bustype == b->bustype) && (a->bus == b->bus) + if ((a->bustype == b->bustype) && (a->parent == b->parent) && (a->path_a == b->path_a) && (a->path_b == b->path_b)) return 1; return 0; @@ -242,12 +240,12 @@ return new_chip; } -struct device *new_device(struct device *parent, struct device *busdev, - struct chip *chip, const int bus, const char *devnum, +struct device *new_device(struct device *parent, struct chip *chip, + const int bustype, const char *devnum, int enabled) { - struct device *new_d = new_dev(parent, busdev); - new_d->bustype = bus; + struct device *new_d = new_dev(parent); + new_d->bustype = bustype; char *tmp; new_d->path_a = strtol(devnum, &tmp, 16); @@ -274,7 +272,7 @@ lastdev->nextdev = new_d; lastdev = new_d; - switch (bus) { + switch (bustype) { case PCI: new_d->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; break; @@ -332,7 +330,7 @@ while (d) { int link = 0; struct device *cmp = d->next_sibling; - while (cmp && (cmp->bus == d->bus) && (cmp->path_a == d->path_a) + while (cmp && (cmp->parent == d->parent) && (cmp->path_a == d->path_a) && (cmp->path_b == d->path_b)) { if (!cmp->used) { if (device_match(d, cmp)) { @@ -468,8 +466,8 @@ fprintf(fil, "#if !DEVTREE_EARLY\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops) ? (ptr->ops) : "0"); fprintf(fil, "#endif\n"); - fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, - ptr->bus->link); + fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->parent->name, + ptr->parent->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); fprintf(fil, "},\n"); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index b707448..49e22ad 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -85,7 +85,6 @@ struct pci_irq_info pci_irq_info[4]; struct device *parent; - struct device *bus; struct device *next; struct device *nextdev; struct device *children; @@ -110,8 +109,8 @@ void postprocess_devtree(void); struct chip *new_chip(char *path); -struct device *new_device(struct device *parent, struct device *busdev, - struct chip *chip, const int bus, const char *devnum, +struct device *new_device(struct device *parent, struct chip *chip, + const int bustype, const char *devnum, int enabled); void alias_siblings(struct device *d); void add_resource(struct device *dev, int type, int index, int base); diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index e0d63d4..e001b31 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -85,7 +85,7 @@ int yylex(); void yyerror(const char *s); -static struct device *cur_parent, *cur_bus; +static struct device *cur_parent; static struct chip *cur_chip; @@ -487,8 +487,8 @@ static const yytype_uint8 yyrline[] = { 0, 36, 36, 36, 38, 38, 38, 38, 40, 40, - 40, 40, 40, 40, 42, 42, 51, 51, 63, 66, - 69, 72, 75 + 40, 40, 40, 40, 42, 42, 51, 51, 61, 64, + 67, 70, 73 }; #endif @@ -1287,7 +1287,7 @@ { case 2: - { cur_parent = cur_bus = head; } + { cur_parent = head; } break; @@ -1318,9 +1318,8 @@ case 16: { - (yyval.device) = new_device(cur_parent, cur_bus, cur_chip, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); + (yyval.device) = new_device(cur_parent, cur_chip, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.device); - cur_bus = (yyval.device); } break; @@ -1329,7 +1328,6 @@ { cur_parent = (yyvsp[-2].device)->parent; - cur_bus = (yyvsp[-2].device)->bus; fold_in((yyvsp[-2].device)); alias_siblings((yyvsp[-2].device)->children); } diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index e8d6fd3..67cc6d3 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -20,7 +20,7 @@ int yylex(); void yyerror(const char *s); -static struct device *cur_parent, *cur_bus; +static struct device *cur_parent; static struct chip *cur_chip; %} @@ -33,7 +33,7 @@ %token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% -devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; +devtree: { cur_parent = head; } chip { postprocess_devtree(); } ; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; @@ -49,13 +49,11 @@ }; device: DEVICE BUS NUMBER /* == devnum */ BOOL { - $<device>$ = new_device(cur_parent, cur_bus, cur_chip, $<number>2, $<string>3, $<number>4); + $<device>$ = new_device(cur_parent, cur_chip, $<number>2, $<string>3, $<number>4); cur_parent = $<device>$; - cur_bus = $<device>$; } devicechildren END { cur_parent = $<device>5->parent; - cur_bus = $<device>5->bus; fold_in($<device>5); alias_siblings($<device>5->children); }; -- To view, visit https://review.coreboot.org/26736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844 Gerrit-Change-Number: 26736 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: src/lib: Remove unneeded 'console.h' include
by Elyes HAOUAS (Code Review) 31 May '18

31 May '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26735 to look at the new patch set (#2). Change subject: src/lib: Remove unneeded 'console.h' include ...................................................................... src/lib: Remove unneeded 'console.h' include Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/timer.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26735/2 -- To view, visit https://review.coreboot.org/26735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Gerrit-Change-Number: 26735 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/lib: Remove unneeded 'console.h' include
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26735 ) Change subject: src/lib: Remove unneeded 'console.h' include ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/73821/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/27935/ : SUCCESS -- To view, visit https://review.coreboot.org/26735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Gerrit-Change-Number: 26735 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 14:45:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL
by build bot (Jenkins) (Code Review) 31 May '18

31 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26349 ) Change subject: soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL ...................................................................... Patch Set 17: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73820/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27934/ : SUCCESS -- To view, visit https://review.coreboot.org/26349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Gerrit-Change-Number: 26349 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 31 May 2018 14:43:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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2013

coreboot-gerrit May 2018