coreboot-gerrit May 2018

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Change in coreboot[master]: i210: Add additional PCI-ID to the i210 driver
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26683 ) Change subject: i210: Add additional PCI-ID to the i210 driver ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73572/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27681/ : SUCCESS -- To view, visit https://review.coreboot.org/26683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37 Gerrit-Change-Number: 26683 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 07:16:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/northbridge: Get rid of whitespace before tab
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26603 ) Change subject: src/northbridge: Get rid of whitespace before tab ...................................................................... Patch Set 7: (14 comments) https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/agesa/family14/… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/agesa/family14/… PS7, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdht/h3gtopo.h… PS7, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbrid… File src/northbridge/amd/amdk8/northbridge.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbrid… PS7, Line 993: if (!is_cpu_pre_e0()) suspect code indent for conditional statements (40, 49) https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbrid… PS7, Line 995: sizek += hoist_memory(mmio_basek, i); line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbrid… PS7, Line 1220: e0_later_single_core = is_e0_later_in_bsp(i); // single core line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/northbrid… PS7, Line 1222: e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/raminit.c File src/northbridge/amd/amdk8/raminit.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdk8/raminit.c… PS7, Line 1310: uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */ line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mct_… File src/northbridge/amd/amdmct/mct/mct_d.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mct_… PS7, Line 3756: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mctd… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct/mctd… PS7, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 7912: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/lx/northbridgei… File src/northbridge/amd/lx/northbridgeinit.c: https://review.coreboot.org/#/c/26603/7/src/northbridge/amd/lx/northbridgei… PS7, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters -- To view, visit https://review.coreboot.org/26603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935 Gerrit-Change-Number: 26603 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 07:13:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: i210: Add additional PCI-ID to the i210 driver
by Werner Zeh (Code Review) 30 May '18

30 May '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/26683 Change subject: i210: Add additional PCI-ID to the i210 driver ...................................................................... i210: Add additional PCI-ID to the i210 driver When the i210 MACPHY is operated in the SERDES Backplane mode (which depends on the programmed firmware image), its PCI-ID will be 0x1537. This does however not change the programming interface for the MAC address. Therefore add this new PCI-ID to the driver so that the MAC address can be programmed in this operation mode as well. Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/intel/i210/i210.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/26683/1 diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index d554745..2eae6a9 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -234,7 +234,7 @@ .ops_pci = 0, }; -static const unsigned short i210_device_ids[] = { 0x1538, 0x1533, 0 }; +static const unsigned short i210_device_ids[] = { 0x1537, 0x1538, 0x1533, 0 }; static const struct pci_driver i210_driver __pci_driver = { .ops = &i210_ops, -- To view, visit https://review.coreboot.org/26683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37 Gerrit-Change-Number: 26683 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: WIP: soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26547 ) Change subject: WIP: soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73558/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27667/ : SUCCESS -- To view, visit https://review.coreboot.org/26547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53 Gerrit-Change-Number: 26547 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 02:15:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Swap PCI devfn resides in same PCI device
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26479 ) Change subject: soc/intel/skylake: Swap PCI devfn resides in same PCI device ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73555/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27664/ : SUCCESS -- To view, visit https://review.coreboot.org/26479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc Gerrit-Change-Number: 26479 Gerrit-PatchSet: 7 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 22:27:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/crossgcc: update to gcc 8.1.0 and binutils 2.30
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

1 0

Change in coreboot[master]: util/crossgcc: update to gcc 8.1.0 and binutils 2.30
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

1 0

Change in coreboot[master]: northbridge/amd/lx: Fix function setShadowRCONF
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20808 ) Change subject: northbridge/amd/lx: Fix function setShadowRCONF ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73553/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27662/ : SUCCESS -- To view, visit https://review.coreboot.org/20808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d7720121d4730254542372282f5561739e7214b Gerrit-Change-Number: 20808 Gerrit-PatchSet: 7 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 21:27:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Swap PCI devfn resides in same PCI device
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26479 ) Change subject: soc/intel/skylake: Swap PCI devfn resides in same PCI device ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73552/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27661/ : SUCCESS -- To view, visit https://review.coreboot.org/26479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc Gerrit-Change-Number: 26479 Gerrit-PatchSet: 6 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 21:27:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Swap PCI devfn resides in same PCI device
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26479 ) Change subject: soc/intel/skylake: Swap PCI devfn resides in same PCI device ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/73551/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/27660/ : SUCCESS -- To view, visit https://review.coreboot.org/26479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc Gerrit-Change-Number: 26479 Gerrit-PatchSet: 5 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 21:19:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit May 2018