coreboot-gerrit May 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: device/oprom/x86emu/prim_ops.c: Fix coding style
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26353 ) Change subject: device/oprom/x86emu/prim_ops.c: Fix coding style ...................................................................... Patch Set 7: (83 comments) https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c File src/device/oprom/x86emu/prim_ops.c: https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 760: if ((cnt = s % 9) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 781: if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ suspect code indent for conditional statements (16, 32) https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 807: if ((cnt = s % 17) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 812: if (ACCESS_FLAG(F_CF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 831: if ((cnt = s % 33) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 878: if ((cnt = s % 9) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 883: /* note hackery here. Access_flag(..) evaluates to either line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 942: if ((cnt = s % 17) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 951: if (ACCESS_FLAG(F_CF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 974: if ((cnt = s % 33) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1021: if ((cnt = s % 8) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1054: if ((cnt = s % 16) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1079: if ((cnt = s % 32) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1119: if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1150: if ((cnt = s % 16) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1173: if ((cnt = s % 32) != 0) { do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1214: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1214: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1250: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1250: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1283: CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1285: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1285: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1318: if (cnt == 1) { braces {} are not necessary for any arm of this statement https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1320: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1320: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1353: if (cnt == 1) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1355: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1355: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1355: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1355: } else { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1387: if (cnt == 1) { braces {} are not necessary for any arm of this statement https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1389: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1389: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1419: if (sf) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1536: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1536: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1569: CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1571: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1571: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1604: if (cnt == 1) { braces {} are not necessary for any arm of this statement https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1606: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1606: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1638: if (cnt == 1) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1640: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1640: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1640: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1640: } else { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1663: if (ACCESS_FLAG(F_CF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1665: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1665: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1665: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1665: } else { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1687: if (ACCESS_FLAG(F_CF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1689: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1689: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1689: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1689: } else { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1711: if (ACCESS_FLAG(F_CF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1713: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1713: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1713: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1713: } else { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1929: if ((d_sign = d & 0x80000000) != 0) do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 1933: if ((s_sign = s & 0x80000000) != 0) do not use assignment in if condition https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2297: } else if (size == 2) { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2297: } else if (size == 2) { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2297: } else if (size == 2) { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2300: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2300: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2300: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2310: if (ACCESS_FLAG(F_DF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2345: } else { code indent should use tabs where possible https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2345: } else { please, no spaces at the start of a line https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2345: } else { space required after that close brace '}' https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2355: if (ACCESS_FLAG(F_DF)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2368: if (M.x86.mode & SYSMODE_32BIT_REP) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2464: /* Regardless if we have real data from the hardware, the emulator line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2465: * will only support upto feature 1, which we set in register EAX. line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2475: /* If we don't have x86 compatible hardware, we return values from an line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2476: * Intel 486dx4; which was one of the first processors to have CPUID. line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2482: /* In the case that we have hardware CPUID instruction, we make sure line over 80 characters https://review.coreboot.org/#/c/26353/7/src/device/oprom/x86emu/prim_ops.c@… PS7, Line 2489: * return all zeros when queried for invalid or unsupported feature line over 80 characters -- To view, visit https://review.coreboot.org/26353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I010f3e02813d38293a7ab7fc84f60b8c2ec098a7 Gerrit-Change-Number: 26353 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 30 May 2018 11:01:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/i945: Add a common function to compute TSEG size
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23448 ) Change subject: nb/intel/i945: Add a common function to compute TSEG size ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73597/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27708/ : SUCCESS -- To view, visit https://review.coreboot.org/23448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Gerrit-Change-Number: 23448 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 11:00:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26566 ) Change subject: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/26566/6/src/include/cpu/x86/mtrr.h File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/#/c/26566/6/src/include/cpu/x86/mtrr.h@145 PS6, Line 145: (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/26566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Gerrit-Change-Number: 26566 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:58:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, nb, soc}/intel: Use CACHE_ROM_BASE where appropriate
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26574 ) Change subject: {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/73595/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/27704/ : SUCCESS -- To view, visit https://review.coreboot.org/26574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Gerrit-Change-Number: 26574 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:56:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26566 ) Change subject: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/73594/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/27703/ : SUCCESS -- To view, visit https://review.coreboot.org/26566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Gerrit-Change-Number: 26566 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:55:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26567 ) Change subject: cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB ...................................................................... Patch Set 5: Verified+1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/27705/ : SUCCESS -- To view, visit https://review.coreboot.org/26567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268 Gerrit-Change-Number: 26567 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:55:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/{amd, intel}: Use CACHE_ROM_(BASE|SIZE)
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26575 ) Change subject: soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE) ...................................................................... Patch Set 4: Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/27706/ : SUCCESS -- To view, visit https://review.coreboot.org/26575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Gerrit-Change-Number: 26575 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:55:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26566 ) Change subject: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/26566/5/src/include/cpu/x86/mtrr.h File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/#/c/26566/5/src/include/cpu/x86/mtrr.h@146 PS5, Line 146: (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/26566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Gerrit-Change-Number: 26566 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:52:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Enable RT5682 headset codec for BIP board
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26211 ) Change subject: mb/google/octopus: Enable RT5682 headset codec for BIP board ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73593/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27702/ : SUCCESS -- To view, visit https://review.coreboot.org/26211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee91518c03a0e9e6ed52bc54a60fc607730a0b7d Gerrit-Change-Number: 26211 Gerrit-PatchSet: 9 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 10:30:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: configure the FPMCU interface
by build bot (Jenkins) (Code Review) 30 May '18

30 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26684 ) Change subject: mb/google/poppy/variants/nocturne: configure the FPMCU interface ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/73587/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/27696/ : SUCCESS -- To view, visit https://review.coreboot.org/26684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 Gerrit-Change-Number: 26684 Gerrit-PatchSet: 1 Gerrit-Owner: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 May 2018 08:42:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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