coreboot-gerrit April 2018

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Change in coreboot[master]: Documentation/Intel: Add MultiProcessorInit documentation
by Subrata Banik (Code Review) 30 Apr '18

30 Apr '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25921 Change subject: Documentation/Intel: Add MultiProcessorInit documentation ...................................................................... Documentation/Intel: Add MultiProcessorInit documentation Add documentation for MP service PPI using EFI interface on Intel 9th Gen Platforms. Documented so far: * Problem Statement * New Design Proposal * API interface * Code Flow changes * Benefits BRANCH=none BUG=b:74436746 TEST=none Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png A Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md 2 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/25921/1 diff --git a/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png b/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png new file mode 100644 index 0000000..5836140 --- /dev/null +++ b/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png Binary files differ diff --git a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md new file mode 100644 index 0000000..6187631 --- /dev/null +++ b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md @@ -0,0 +1,74 @@ +# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI + +## Introduction + +This documentation is intended to document the purpose for creating EFI service +Interface inside Coreboot space to perform CPU feature programming on Application +Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs. + +Today Coreboot is capable enough to handle multi-processor initialization on IA platforms. + +The multi-processor initialization code has to take care of lots of duties: + +1 Bringing all cores out of reset +2 Load latest microcode on all cores +3 Sync latest MTRR snapshot between BSP and APs +4 Perform sets of CPU feature programming + * CPU Power & Thermal Management + * Overclocking + * Intel Trusted Execution Technology + * Intel Software Guard Extensions + * Intel Processor Trace etc. + +This above CPU feature programming lists are expected to grow with current and future +CPU complexity and there might be some cases where certain feature programming mightbe +closed source in nature. + +Platform code might need to compromise on those closed source nature of CPU programming +if we don't plan to provide an alternate interface which can be used by Coreboot to +get-rid of such close source CPU programming. + +## Proposal + +As Coreboot is doing CPU multi-processor initialization for IA platform before FSP-S +initialization and having all possible information about cores in terms of maximum number +of cores, APIC ids, stack size etc. It’s also possible for Coreboot to extend its own +support model and create a sets of APIs which later can be used by FSP to run CPU feature +programming using Coreboot published APIs. + +Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate +PPI to perform certain API call, hence Coreboot has to created MP services APIs known as +EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9. +More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf + +### Coreboot to publish EFI_MP_SERVICES_PPI APIs +| API | Description | +|------------------------------|------------------------------------------------------------------| +| PeiGetNumberOfProcessors | Get the number of CPU's. | +| PeiGetProcessorInfo | Get information on a specific CPU. | +| PeiStartupAllAPs | Activate all of the application processors. | +| PeiStartupThisAP | Activate a specific application processor. | +| PeiSwitchBSP | Switch the boot strap processor. | +| PeiEnableDisableAP | Enable or disable an application processor. | +| PeiWhoAmI | Identify the currently executing processor. | +|------------------------------|------------------------------------------------------------------| + + +## Code Flow + +Here is proposed design flow with Coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make +use of the same to perform some CPU feature programming. + +** Coreboot-FSP MP init flow ** +![alt text][Coreboot_Publish_MP_Service_API] + +[Coreboot_Publish_MP_Service_API]: Coreboot_Publish_MP_Service_API.png "Coreboot-FSP MP init flow" + +## Benefits +1. Coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming. +With proposed model, Coreboot will make use of SkipMpInit=0 which will allow to run all +Silicon recommended CPU programming. +2. CPU feature programming inside FSP will be more transparent than before as it’s using +Coreboot interfaces to execute those programming. +3. Coreboot will have more control over running those feature programming as API optimization +handled by Coreboot. -- To view, visit https://review.coreboot.org/25921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Gerrit-Change-Number: 25921 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mainboard/google/kahlee: Pass oscout system clk to da7219
by Akshu Agrawal (Code Review) 30 Apr '18

30 Apr '18

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/25920 Change subject: mainboard/google/kahlee: Pass oscout system clk to da7219 ...................................................................... mainboard/google/kahlee: Pass oscout system clk to da7219 Using da7219 mclk-name property, oscout system clock is linked to da7219 mclk. da7219 then handles enabling/disabling of the clk. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/mainboard/google/kahlee/variants/grunt/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/25920/1 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index cfc3198..c823825 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -104,6 +104,7 @@ register "adc_1bit_rpt" = "1" register "micbias_lvl" = "2600" register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" device i2c 1a on end end chip drivers/generic/max98357a -- To view, visit https://review.coreboot.org/25920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Gerrit-Change-Number: 25920 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com>

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Change in coreboot[master]: drivers/i2c/da7219: Add mclk-name property
by Akshu Agrawal (Code Review) 30 Apr '18

30 Apr '18

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/25919 Change subject: drivers/i2c/da7219: Add mclk-name property ...................................................................... drivers/i2c/da7219: Add mclk-name property Non-dts based systems can pass mclk to da7219 driver by this property. BUG=b:74570989 TEST=Enabled clock in kernel driver using the property Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/drivers/i2c/da7219/chip.h M src/drivers/i2c/da7219/da7219.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/25919/1 diff --git a/src/drivers/i2c/da7219/chip.h b/src/drivers/i2c/da7219/chip.h index 572d727..deb1c26 100644 --- a/src/drivers/i2c/da7219/chip.h +++ b/src/drivers/i2c/da7219/chip.h @@ -106,4 +106,10 @@ * [<1>, <2>, <4>, <8>] */ unsigned adc_1bit_rpt; + + /* + * mclk-name : Pass the system clk to da7219 + * ["name of mclk" ] + */ + const char *mclk_name; }; diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index c0f152d..10d9152 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -86,6 +86,7 @@ dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_integer(dsd, "dlg,micbias-lvl", config->micbias_lvl); acpi_dp_add_string(dsd, "dlg,mic-amp-in-sel", config->mic_amp_in_sel); + acpi_dp_add_string(dsd, "dlg,mclk-name", config->mclk_name); acpi_dp_add_child(dsd, "da7219_aad", aad); /* Write Device Property Hierarchy */ -- To view, visit https://review.coreboot.org/25919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb Gerrit-Change-Number: 25919 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com>

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Change in coreboot[master]: soc/amd/stonyridge: Add misc device
by Akshu Agrawal (Code Review) 30 Apr '18

30 Apr '18

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/25918 Change subject: soc/amd/stonyridge: Add misc device ...................................................................... soc/amd/stonyridge: Add misc device oscout system clock is present in FCH misc device. The kernel acpi misc driver will use the resource to register oscout system clock. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16 Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/soc/amd/stoneyridge/acpi/sb_fch.asl 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/25918/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 2ffd951..3a4839e 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -137,3 +137,16 @@ Return (0x0F) } } + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} -- To view, visit https://review.coreboot.org/25918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16 Gerrit-Change-Number: 25918 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com>

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Change in coreboot[master]: chromeec platforms: Update ACPI thermal event handler call
by Martin Roth (Code Review) 30 Apr '18

30 Apr '18

Martin Roth has uploaded a new patch set (#2). ( https://review.coreboot.org/25916 ) Change subject: chromeec platforms: Update ACPI thermal event handler call ...................................................................... chromeec platforms: Update ACPI thermal event handler call Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl M src/soc/intel/baytrail/acpi/dptf/thermal.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl M src/soc/intel/common/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl 6 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/25916/2 -- To view, visit https://review.coreboot.org/25916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Gerrit-Change-Number: 25916 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: chromeec platforms: Update ACPI thermal event handler call
by Martin Roth (Code Review) 30 Apr '18

30 Apr '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25916 Change subject: chromeec platforms: Update ACPI thermal event handler call ...................................................................... chromeec platforms: Update ACPI thermal event handler call Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl M src/soc/intel/baytrail/acpi/dptf/thermal.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl M src/soc/intel/common/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl 6 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/25916/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 62f9acd..9ec5f7f 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -21,7 +21,6 @@ // Mainboard specific throttle handler External (\_TZ.THRT, MethodObj) -External (\_SB.DPTF.TEVT, MethodObj) #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) #endif @@ -481,9 +480,9 @@ /* When sensor ID returns 0xFF then no more events */ While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) { - If (CondRefOf (\_SB.DPTF.TEVT)) { - \_SB.DPTF.TEVT (Local0) - } +#ifdef HAVE_THERM_EVENT_HANDLER + \_SB.DPTF.TEVT (Local0) +#endif /* Keep reaading sensor ID for event */ Store (^PATI, Local0) diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl index 6879076..1ff308d 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -15,6 +15,7 @@ */ /* Thermal Threshold Event Handler */ +#define HAVE_THERM_EVENT_HANDLER Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl index 00dc964..6fa8eea 100644 --- a/src/soc/intel/baytrail/acpi/dptf/thermal.asl +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -12,7 +12,9 @@ * GNU General Public License for more details. */ + /* Thermal Threshold Event Handler */ +#define HAVE_THERM_EVENT_HANDLER Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 5d685bb..e104756 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -13,6 +13,7 @@ */ /* Thermal Threshold Event Handler */ +#define HAVE_THERM_EVENT_HANDLER Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index ce220c4..c8aa037 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -15,6 +15,7 @@ */ /* Thermal Threshold Event Handler */ +#define HAVE_THERM_EVENT_HANDLER Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index d84807b..8290392 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -15,6 +15,7 @@ */ /* Thermal Threshold Event Handler */ +#define HAVE_THERM_EVENT_HANDLER Method (TEVT, 1, NotSerialized) { -- To view, visit https://review.coreboot.org/25916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Gerrit-Change-Number: 25916 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable synaptics TouchScreen support
by Ivy Jian (Code Review) 30 Apr '18

30 Apr '18

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/25915 Change subject: mb/google/poppy/variants/nami: Enable synaptics TouchScreen support ...................................................................... mb/google/poppy/variants/nami: Enable synaptics TouchScreen support BUG=b:74595040 BRANCH=master TEST=NONE Change-Id: Ic11684d5ed961af5eb704909f7d06eb0898068c2 Signed-off-by: ivy_jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/25915/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index b1c278c..a50b5f7 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -262,6 +262,18 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "generic.enable_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end end # I2C #0 device pci 15.1 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/25915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic11684d5ed961af5eb704909f7d06eb0898068c2 Gerrit-Change-Number: 25915 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com>

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Change in coreboot[master]: Fix freeze during chipset lockdown on Nehalem
by Matthias Gazzari (Code Review) 30 Apr '18

30 Apr '18

Matthias Gazzari has uploaded this change for review. ( https://review.coreboot.org/25914 Change subject: Fix freeze during chipset lockdown on Nehalem ...................................................................... Fix freeze during chipset lockdown on Nehalem Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c) and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue which became apparent with commit d533b16669a3bacb19b2824e6b4bc76a2a18c92a. More detailed, either setting the LSB of the 32 bit register at 0x98 of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the intel_model_2065x_finalize_smm function) indepentenly causes a freeze during bootup or a complete session loss on resuming from S3 as described here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register. Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series, Datasheet Volume Two" indicates that registers of the PCI device 00:00.0 cannot be locked manually. Instead, they can only be locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK. Finally, the addresses and sizes of these registers were partially wrong. Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT support compared to the Core i5 and Core i7 processors of a X201). Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b Signed-off-by: Matthias Gazzari <mail(a)qtux.eu> --- M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_2065x/model_2065x.h M src/northbridge/intel/nehalem/finalize.c 3 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25914/1 diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 50e00bf..5e7b3d8 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -54,7 +54,4 @@ /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); - - /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8bb3b87..f87ba77 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -39,7 +39,6 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index f90f937..7313840 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -23,18 +23,6 @@ void intel_nehalem_finalize_smm(void) { - pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ -- To view, visit https://review.coreboot.org/25914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b Gerrit-Change-Number: 25914 Gerrit-PatchSet: 1 Gerrit-Owner: Matthias Gazzari <mail(a)qtux.eu>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable Synaptics touchpad
by Furquan Shaikh (Code Review) 30 Apr '18

30 Apr '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/25913 ) Change subject: mb/google/poppy/variants/nami: Enable Synaptics touchpad ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/25913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Gerrit-Change-Number: 25913 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 30 Apr 2018 02:26:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable Synaptics touchpad
by Ivy Jian (Code Review) 30 Apr '18

30 Apr '18

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/25913 Change subject: mb/google/poppy/variants/nami: Enable Synaptics touchpad ...................................................................... mb/google/poppy/variants/nami: Enable Synaptics touchpad BUG=b:74595037 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: PNP0C50:00 06CB:CD84 Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Signed-off-by: ivy_jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/25913/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index b1c278c..c7a4c05 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -271,6 +271,15 @@ register "wake" = "GPE0_DW2_16" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "generic.wake" = "GPE0_DW2_16" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end # I2C #1 device pci 15.2 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/25913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Gerrit-Change-Number: 25913 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com>

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