coreboot-gerrit April 2018

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Change in coreboot[master]: intel/common: compress VBT
by Patrick Georgi (Code Review) 30 Apr '18

30 Apr '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/25927 Change subject: intel/common: compress VBT ...................................................................... intel/common: compress VBT It's pretty well compressible which helps when space is tight. The code encodes the assumption that the VBT is 8kb or less. Haven't seen a larger one yet. BUG=b:77971803,b:78541692 TEST=build, see that vbt.bin is compressed, boot, check log that the reported VBT size is correct. Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/drivers/intel/gma/Makefile.inc M src/soc/intel/common/vbt.c 2 files changed, 14 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25927/1 diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index ab799ef..0bcf590 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -24,6 +24,7 @@ cbfs-files-$(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE) += vbt.bin vbt.bin-file := $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE)) vbt.bin-type := raw +vbt.bin-compression := lzma ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 3d8f2bf..1e591a0 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -30,34 +30,34 @@ return "vbt.bin"; } -static struct region_device vbt_rdev; -static void *vbt_data; +static char vbt_data[8192]; +static int vbt_data_used = 0; void *locate_vbt(void) { uint32_t vbtsig = 0; - struct cbfsf file_desc; - if (vbt_data != NULL) - return vbt_data; + if (vbt_data_used == 1) + return (void *)vbt_data; const char *filename = mainboard_vbt_filename(); - if (cbfs_boot_locate(&file_desc, filename, NULL) < 0) { - printk(BIOS_ERR, "Could not locate a VBT file in in CBFS\n"); + size_t file_size = cbfs_boot_load_file(filename, + vbt_data, sizeof(vbt_data), CBFS_TYPE_RAW); + + if (file_size == 0) return NULL; - } - cbfs_file_data(&vbt_rdev, &file_desc); - rdev_readat(&vbt_rdev, &vbtsig, 0, sizeof(uint32_t)); - + memcpy((void *)&vbtsig, vbt_data, sizeof(vbtsig)); if (vbtsig != VBT_SIGNATURE) { printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n"); return NULL; } - vbt_data = rdev_mmap_full(&vbt_rdev); - return vbt_data; + printk(BIOS_INFO, "Found a VBT of %zd bytes after decompression\n", file_size); + vbt_data_used = 1; + + return (void *)vbt_data; } void *vbt_get(void) @@ -73,11 +73,3 @@ return NULL; return locate_vbt(); } - -static void unmap_vbt(void *unused) -{ - if (vbt_data) - rdev_munmap(&vbt_rdev, vbt_data); -} -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, unmap_vbt, NULL); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, unmap_vbt, NULL); -- To view, visit https://review.coreboot.org/25927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4 Gerrit-Change-Number: 25927 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: lenovo: Add various vbt.bin
by Nico Huber (Code Review) 30 Apr '18

30 Apr '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/25926 ) Change subject: lenovo: Add various vbt.bin ...................................................................... Patch Set 1: Code-Review+1 (2 comments) +2 for all but T400 https://review.coreboot.org/#/c/25926/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25926/1//COMMIT_MSG@10 PS1, Line 10: coreboot's blob free graphics init. No line break or start a new paragraph. https://review.coreboot.org/#/c/25926/1/src/mainboard/lenovo/t400/vbt.bin File src/mainboard/lenovo/t400/vbt.bin: PS1: Lenovo shipped two different BIOS versions for the X200 (one for LED backlight, one for CCFL). Same might be true for the T400. If that's the case, we should either add runtime detection / patching of VBT or a Kconfig choice for the variant. -- To view, visit https://review.coreboot.org/25926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48 Gerrit-Change-Number: 25926 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 30 Apr 2018 12:57:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: lenovo: Add various vbt.bin
by Patrick Rudolph (Code Review) 30 Apr '18

30 Apr '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25926 Change subject: lenovo: Add various vbt.bin ...................................................................... lenovo: Add various vbt.bin Add the Video Bios Table to improve user experience when running coreboot's blob free graphics init. As it's not a binary blob it should not be added to the blobs repo. This is taken from vendor BIOS and contains purely documented configuration data, so it should not be subjected to copyright. Extracted using intelvbttool with applied patch I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool" Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/mainboard/lenovo/t400/vbt.bin A src/mainboard/lenovo/t420/vbt.bin A src/mainboard/lenovo/t420s/vbt.bin A src/mainboard/lenovo/t430/vbt.bin A src/mainboard/lenovo/t430s/vbt.bin A src/mainboard/lenovo/t520/vbt.bin A src/mainboard/lenovo/t530/vbt.bin A src/mainboard/lenovo/x220/vbt.bin A src/mainboard/lenovo/x230/vbt.bin 9 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25926/1 diff --git a/src/mainboard/lenovo/t400/vbt.bin b/src/mainboard/lenovo/t400/vbt.bin new file mode 100644 index 0000000..fee6e4c --- /dev/null +++ b/src/mainboard/lenovo/t400/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/t420/vbt.bin b/src/mainboard/lenovo/t420/vbt.bin new file mode 100644 index 0000000..ba867b7 --- /dev/null +++ b/src/mainboard/lenovo/t420/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/t420s/vbt.bin b/src/mainboard/lenovo/t420s/vbt.bin new file mode 100644 index 0000000..528e794 --- /dev/null +++ b/src/mainboard/lenovo/t420s/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/t430/vbt.bin b/src/mainboard/lenovo/t430/vbt.bin new file mode 100644 index 0000000..7593154 --- /dev/null +++ b/src/mainboard/lenovo/t430/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/t430s/vbt.bin b/src/mainboard/lenovo/t430s/vbt.bin new file mode 100644 index 0000000..7593154 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/t520/vbt.bin b/src/mainboard/lenovo/t520/vbt.bin new file mode 100644 index 0000000..fcfd3c2 --- /dev/null +++ b/src/mainboard/lenovo/t520/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/t530/vbt.bin b/src/mainboard/lenovo/t530/vbt.bin new file mode 100644 index 0000000..2974332 --- /dev/null +++ b/src/mainboard/lenovo/t530/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/x220/vbt.bin b/src/mainboard/lenovo/x220/vbt.bin new file mode 100644 index 0000000..2b5bc1e --- /dev/null +++ b/src/mainboard/lenovo/x220/vbt.bin Binary files differ diff --git a/src/mainboard/lenovo/x230/vbt.bin b/src/mainboard/lenovo/x230/vbt.bin new file mode 100644 index 0000000..0f50d70 --- /dev/null +++ b/src/mainboard/lenovo/x230/vbt.bin Binary files differ -- To view, visit https://review.coreboot.org/25926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48 Gerrit-Change-Number: 25926 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: gitignore: Remove .bin
by Patrick Rudolph (Code Review) 30 Apr '18

30 Apr '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25925 Change subject: gitignore: Remove .bin ...................................................................... gitignore: Remove .bin Allow the use of binary (data) files in coreboot src/ tree. Change-Id: I27bd5890a3f79c5e0e589772789cc30ec51b2b3b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M .gitignore 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25925/1 diff --git a/.gitignore b/.gitignore index 378741f..4e659aa 100644 --- a/.gitignore +++ b/.gitignore @@ -53,7 +53,6 @@ site-local *.\# -*.bin *.debug *.elf *.o -- To view, visit https://review.coreboot.org/25925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I27bd5890a3f79c5e0e589772789cc30ec51b2b3b Gerrit-Change-Number: 25925 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/google/fizz: Tune DPTF settings
by Sumeet R Pawnikar (Code Review) 30 Apr '18

30 Apr '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/25924 Change subject: mb/google/fizz: Tune DPTF settings ...................................................................... mb/google/fizz: Tune DPTF settings This patch reduces tcc_offset value from 6 to 0. Also, set the CPU critical temperature threshold to 105 degree celcius from 100. These are the fine tuned values to avoid the over heating condition. Change-Id: Ia0e4e054e68a9059f38934ec0d39cb5c2c24f043 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/fizz/acpi/dptf.asl M src/mainboard/google/fizz/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/25924/1 diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl index f877c71..fb7cf91 100644 --- a/src/mainboard/google/fizz/acpi/dptf.asl +++ b/src/mainboard/google/fizz/acpi/dptf.asl @@ -15,7 +15,7 @@ */ #define DPTF_CPU_PASSIVE 93 -#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 77 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 9d120ea..1f11060 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -312,7 +312,7 @@ register "speed_shift_enable" = "1" register "tdp_psyspl2" = "90" register "psys_pmax" = "120" - register "tcc_offset" = "6" # TCC of 94C + register "tcc_offset" = "0" # TCC of 100C # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" -- To view, visit https://review.coreboot.org/25924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia0e4e054e68a9059f38934ec0d39cb5c2c24f043 Gerrit-Change-Number: 25924 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming ...
by Subrata Banik (Code Review) 30 Apr '18

30 Apr '18

Subrata Banik has uploaded a new patch set (#3). ( https://review.coreboot.org/25923 ) Change subject: mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs ...................................................................... mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs This patch ensures that FSP can make use of PPI infrastructure in order to run closed source CPU feature programming over APs during FSP-Silicon initialization. BRANCH=none BUG=b:74436746 TEST=Verify CPU feature programming is using coreboot APIs. Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25923/3 -- To view, visit https://review.coreboot.org/25923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297 Gerrit-Change-Number: 25923 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: fsp2_0/cannonlake: Add MP services UPDs into FSP-S header
by Subrata Banik (Code Review) 30 Apr '18

30 Apr '18

Subrata Banik has uploaded a new patch set (#3). ( https://review.coreboot.org/25922 ) Change subject: fsp2_0/cannonlake: Add MP services UPDs into FSP-S header ...................................................................... fsp2_0/cannonlake: Add MP services UPDs into FSP-S header Add 2 FSP-S UPD to make use of coreboot MP service PPI structure * CpuMpPpi - Pointer to MP service PPI * CpuInitMpLibHob - Pointer for CPU data Hob [N/A for coreboot] BRANCH=none BUG=b:74436746 TEST=None Change-Id: I7eddc650c78777504768e7820ec04742908ac77a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 1 file changed, 22 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/25922/3 -- To view, visit https://review.coreboot.org/25922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7eddc650c78777504768e7820ec04742908ac77a Gerrit-Change-Number: 25922 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: Documentation/Intel: Add MultiProcessorInit documentation
by Subrata Banik (Code Review) 30 Apr '18

30 Apr '18

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/25921 ) Change subject: Documentation/Intel: Add MultiProcessorInit documentation ...................................................................... Documentation/Intel: Add MultiProcessorInit documentation Add documentation for MP service PPI using EFI interface on Intel 9th Gen Platforms. Documented so far: * Problem Statement * New Design Proposal * API interface * Code Flow changes * Benefits BRANCH=none BUG=b:74436746 TEST=none Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png A Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md 2 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/25921/2 -- To view, visit https://review.coreboot.org/25921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Gerrit-Change-Number: 25921 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming ...
by Subrata Banik (Code Review) 30 Apr '18

30 Apr '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25923 Change subject: mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs ...................................................................... mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs This patch ensures that FSP can make use of PPI infrastructure in order to run closed source CPU feature programming over APs during FSP-Silicon initialization. BRANCH=none BUG=b:74436746 TEST=Verify CPU feature programming is using coreboot APIs. Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25923/1 diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 512354e..f336d91 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -20,7 +20,7 @@ # FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" + register "FspSkipMpInit" = "0" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 4076ea6..6a20f1c 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -29,7 +29,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "FspSkipMpInit" = "1" + register "FspSkipMpInit" = "0" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 18aa65d..e1b45d9 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -6,7 +6,7 @@ # FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" + register "FspSkipMpInit" = "0" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 8bcb850..9b19a90 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -6,7 +6,7 @@ # FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" + register "FspSkipMpInit" = "0" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" -- To view, visit https://review.coreboot.org/25923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297 Gerrit-Change-Number: 25923 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: fsp2_0/cannonlake: Add MP services UPDs into FSP-S header
by Subrata Banik (Code Review) 30 Apr '18

30 Apr '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25922 Change subject: fsp2_0/cannonlake: Add MP services UPDs into FSP-S header ...................................................................... fsp2_0/cannonlake: Add MP services UPDs into FSP-S header Add 2 FSP-S UPD to make use of coreboot MP service PPI structure * CpuMpPpi - Pointer to MP service PPI * CpuInitMpLibHob - Pointer for CPU data Hob [N/A for coreboot] BRANCH=none BUG=b:74436746 TEST=None Change-Id: I7eddc650c78777504768e7820ec04742908ac77a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 1 file changed, 22 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/25922/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 4daf891..14fa8cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -1093,22 +1093,25 @@ **/ UINT16 ImonSlope1[5]; -/** Offset 0x0324 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. +/** Offset 0x0324 - CpuMpPpi + Pointer for CpuMpPpi **/ - UINT32 VrPowerDeliveryDesign; + UINT32 CpuMpPpi; -/** Offset 0x0328 - ReservedCpuPostMemProduction +/** Offset 0x0328 - CpuInitMpLibHob + Pointer for CpuInitMpLibHob +**/ + UINT32 CpuInitMpLibHob; + +/** Offset 0x032C - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ UINT8 ReservedCpuPostMemProduction[1]; -/** Offset 0x0329 +/** Offset 0x032D **/ - UINT8 UnusedUpdSpace10[29]; + UINT8 UnusedUpdSpace10[25]; /** Offset 0x0346 - Enable DMI ASPM Deprecated. @@ -1876,6 +1879,7 @@ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. + 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU **/ UINT8 PchSerialIoI2cPadsTermination[6]; @@ -2154,17 +2158,9 @@ **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS +/** Offset 0x0752 **/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x0753 -**/ - UINT8 UnusedUpdSpace25; + UINT8 UnusedUpdSpace25[2]; /** Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2297,7 +2293,7 @@ **/ UINT8 ChapDeviceEnable; -/** Offset 0x07B2 - Skip PAM register lock +/** Offset 0x07B2 - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS @@ -2480,7 +2476,7 @@ /** Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; <b>0: Disabled</b>; 1: Enabled. + target; 0: Disabled; <b>1: Enabled </b>. $EN_DIS **/ UINT8 TccOffsetLock; @@ -2844,10 +2840,9 @@ **/ UINT16 PsysPmax; -/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF +/** Offset 0x0858 **/ - UINT16 CstateLatencyControl0Irtl; + UINT8 Reserved0[2]; /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF @@ -2894,13 +2889,13 @@ /** Offset 0x0870 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 + Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit4; /** Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 + Range 0 to 4095875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; @@ -3089,7 +3084,8 @@ UINT8 PchUnlockGpioPads; /** Offset 0x08C2 - PCH Unlock SBI access - Deprecated + This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1: + Unlock SBI access. $EN_DIS **/ UINT8 PchSbiUnlock; -- To view, visit https://review.coreboot.org/25922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7eddc650c78777504768e7820ec04742908ac77a Gerrit-Change-Number: 25922 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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coreboot-gerrit April 2018