[coreboot] Lenovo X201i not booting and not resuming from S3 due to SMM finalize

[qtux]

Hello,

I found that after updating my Lenovo X201i the commit
d533b16669a3bacb19b2824e6b4bc76a2a18c92a [1] causes a freeze during
boot. Additionally, if INTEL_CHIPSET_LOCKDOWN is disabled (and thus
booting works), resuming from S3 does not work anymore. I found that the
following patch circumvents the S3 resume issue (I did not test with
INTEL_CHIPSET_LOCKDOWN enabled, yet):

diff --git a/src/cpu/intel/model_2065x/finalize.c
b/src/cpu/intel/model_2065x/finalize.c
index 50e00bf74a..693aafe37a 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -56,5 +56,5 @@ void intel_model_2065x_finalize_smm(void)
        msr_set_bit(MSR_MISC_PWR_MGMT, 22);

        /* Lock memory configuration to protect SMM */
-       msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
+       //msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/northbridge/intel/nehalem/finalize.c
b/src/northbridge/intel/nehalem/finalize.c
index 0b5cb74ce2..c9bce581bf 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -26,7 +26,7 @@ void intel_nehalem_finalize_smm(void)
        pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);     /* DPR */
        pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10);    /* ME */
        pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0);     /* REMAPBASE */
-       pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);     /* REMAPLIMIT */
+       //pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);   /* REMAPLIMIT */
        pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0);     /* TOM */
        pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0);     /* TOUUD */
        pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0);     /* BDSM */

I tried to find some clues in the documentation of the first [2] and
second [3] generation mobile Core CPU as the finalize code seems to be
copied from the Sandy Bridge code. I found no reference to a register
locking mechanism in [2] comparable to the one described in [3] and used
inside the SMM finalization code, which seems odd to me. Additionally,
the register sizes and locations appear to be different. I suspect that
the Nehalem finalize function does not work as intended and may probably
be removed altogether.

Do you have any ideas on what is wrong here? I added my shortconfig [4]
in case you need it.

Cheers,
Matthias

[1] https://review.coreboot.org/21129
[2]
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-core-family-mobile-vol-2-datasheet.pdf
[3]
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/core-mobile-datasheet-vol-2.pdf
[4] shortconfig:
# This image was built using coreboot 4.7-784-g08c4ce851e-dirty
CONFIG_VENDOR_LENOVO=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_HAVE_ME_BIN=y
CONFIG_HAVE_GBE_BIN=y
CONFIG_BOARD_LENOVO_X201=y
# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y