coreboot-gerrit April 2018

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Change in coreboot[master]: amd/stoneyridge: Add GNB IOAPIC init
by Marc Jones (Code Review) 06 Apr '18

06 Apr '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/25541 Change subject: amd/stoneyridge: Add GNB IOAPIC init ...................................................................... amd/stoneyridge: Add GNB IOAPIC init Use standard coreboot function to set virtual wire mode on the GNB IOAPIC. BUG=b:74104946 TEST=Check GNB IOAPIC debug output on serial. Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25541/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c640c1f..b725f9e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -15,6 +15,7 @@ #include <arch/io.h> +#include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/acpigen.h> #include <cbmem.h> @@ -69,12 +70,20 @@ static void read_resources(device_t dev) { + struct resource *res; + /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) @@ -165,6 +174,7 @@ static void northbridge_init(struct device *dev) { + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) -- To view, visit https://review.coreboot.org/25541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Gerrit-Change-Number: 25541 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: ioapic: extend definition name to avoid collision
by Marc Jones (Code Review) 06 Apr '18

06 Apr '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/25540 Change subject: ioapic: extend definition name to avoid collision ...................................................................... ioapic: extend definition name to avoid collision Change EN/DISABLED to INT_EN/DISABLED to avoid colission with other EN/DISABLE definition. Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> --- M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/drivers/generic/ioapic/ioapic.c 3 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/25540/1 diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index ad96ba3..bc229d9 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -26,8 +26,8 @@ #define ALL (0xff << 24) #define NONE (0) -#define DISABLED (1 << 16) -#define ENABLED (0 << 16) +#define INT_DISABLED (1 << 16) +#define INT_ENABLED (0 << 16) #define TRIGGER_EDGE (0 << 15) #define TRIGGER_LEVEL (1 << 15) #define POLARITY_HIGH (0 << 13) diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index dba49c0..7bd52f5 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -53,7 +53,7 @@ ioapic_interrupts = ioapic_interrupt_count(ioapic_base); - low = DISABLED; + low = INT_DISABLED; high = NONE; for (i = 0; i < ioapic_interrupts; i++) { @@ -118,7 +118,7 @@ } /* Enable Virtual Wire Mode. */ - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); io_apic_write(ioapic_base, 0x10, low); @@ -131,7 +131,7 @@ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); - low = DISABLED; + low = INT_DISABLED; high = NONE; for (i = 1; i < ioapic_interrupts; i++) { io_apic_write(ioapic_base, i * 2 + 0x10, low); diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 44f1b02..271e98c 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -61,7 +61,7 @@ if (config->enable_virtual_wire) { /* Enable Virtual Wire Mode. */ - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); io_apic_write(ioapic_base, 0x10, low); @@ -75,7 +75,7 @@ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); } - low = DISABLED; + low = INT_DISABLED; high = NONE; for (i = 1; i < ioapic_interrupts; i++) { -- To view, visit https://review.coreboot.org/25540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef Gerrit-Change-Number: 25540 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: mb/google/octopus: Edge trigger cr50 interrupt
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25538 ) Change subject: mb/google/octopus: Edge trigger cr50 interrupt ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69548/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23860/ : SUCCESS -- To view, visit https://review.coreboot.org/25538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Gerrit-Change-Number: 25538 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Apr 2018 21:06:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Edge trigger cr50 interrupt
by Justin TerAvest (Code Review) 05 Apr '18

05 Apr '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25538 Change subject: mb/google/octopus: Edge trigger cr50 interrupt ...................................................................... mb/google/octopus: Edge trigger cr50 interrupt Interrupts from cr50 are edge-triggered, not level-triggered. This change updates the GPIO configuration accordingly. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25538/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 3d5d925..8fe1205 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -87,7 +87,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */ @@ -264,7 +264,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ /* GSPI0_INT */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ /* GSPI0_CLK */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ -- To view, visit https://review.coreboot.org/25538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Gerrit-Change-Number: 25538 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: soc/intel/apollolake: Set GLK LPSS clock to 100MHz
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25537 ) Change subject: soc/intel/apollolake: Set GLK LPSS clock to 100MHz ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69547/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23859/ : SUCCESS -- To view, visit https://review.coreboot.org/25537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d6201ca7ba0f0016178aea56243eba90fc570c6 Gerrit-Change-Number: 25537 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Apr 2018 20:46:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Set GLK LPSS clock to 100MHz
by Justin TerAvest (Code Review) 05 Apr '18

05 Apr '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25537 Change subject: soc/intel/apollolake: Set GLK LPSS clock to 100MHz ...................................................................... soc/intel/apollolake: Set GLK LPSS clock to 100MHz The LPSS clock speed setting is incorrect for GLK; the value has changed from 133MHz to 100MHz. BUG=b:75306520 BRANCH=None TEST=Measured SPI communication at intended 1MHz on GLK w/ scope Change-Id: I4d6201ca7ba0f0016178aea56243eba90fc570c6 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25537/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index fcb1ef7..e9d9c39 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -161,7 +161,8 @@ config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ int - default 133 + default 133 if !SOC_INTEL_GLK + default 100 if SOC_INTEL_GLK config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int -- To view, visit https://review.coreboot.org/25537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4d6201ca7ba0f0016178aea56243eba90fc570c6 Gerrit-Change-Number: 25537 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: soc/intel/apollolake: for GLK enable HDA
by Hannah Williams (Code Review) 05 Apr '18

05 Apr '18

Hannah Williams has abandoned this change. ( https://review.coreboot.org/19825 ) Change subject: soc/intel/apollolake: for GLK enable HDA ...................................................................... Abandoned already done -- To view, visit https://review.coreboot.org/19825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ieb8866b4f9cd177ca4947b875134e4dbbbf94cb1 Gerrit-Change-Number: 19825 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com>

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Change in coreboot[master]: mainboard/intel/glkrvp: Turn on Fan
by Hannah Williams (Code Review) 05 Apr '18

05 Apr '18

Hannah Williams has abandoned this change. ( https://review.coreboot.org/20931 ) Change subject: mainboard/intel/glkrvp: Turn on Fan ...................................................................... Abandoned was already done in another commit -- To view, visit https://review.coreboot.org/20931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I2b5ef9fabb9fa1b5e0501247c720f6c8dd22d509 Gerrit-Change-Number: 20931 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Add check for invalid dev value
by Hannah Williams (Code Review) 05 Apr '18

05 Apr '18

Hannah Williams has abandoned this change. ( https://review.coreboot.org/22764 ) Change subject: soc/intel/apollolake: Add check for invalid dev value ...................................................................... Abandoned Not needed -- To view, visit https://review.coreboot.org/22764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ic713a4d18499dcdf7f485e0d8521d2aaeb1f0308 Gerrit-Change-Number: 22764 Gerrit-PatchSet: 1 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add SPD file for Vayne
by build bot (Jenkins) (Code Review) 05 Apr '18

05 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25461 ) Change subject: mb/google/poppy/variants/nami: Add SPD file for Vayne ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69546/ : SUCCESS -- To view, visit https://review.coreboot.org/25461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Gerrit-Change-Number: 25461 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: luke yang <luke_yang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 05 Apr 2018 16:07:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit April 2018