coreboot-gerrit April 2018

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Change in coreboot[master]: util/cbfstool: Print all supported architectures
by Jonathan Neuschäfer (Code Review) 10 Apr '18

10 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25590 Change subject: util/cbfstool: Print all supported architectures ...................................................................... util/cbfstool: Print all supported architectures The list of supported architectures in the usage output of cbfstool is currently hardcoded and outdated. Use the arch_names array in common.c to provide and up-to-date list. Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M util/cbfstool/cbfstool.c M util/cbfstool/common.c M util/cbfstool/common.h 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/25590/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 1f71906..7156e00 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1350,10 +1350,11 @@ " in two possible formats: if their value is greater than\n" " 0x80000000, they are interpreted as a top-aligned x86 memory\n" " address; otherwise, they are treated as an offset into flash.\n" - "ARCHes:\n" - " arm64, arm, mips, x86\n" - "TYPEs:\n", name, name + "ARCHes:\n", name, name ); + print_supported_architectures(); + + printf("TYPEs:\n"); print_supported_filetypes(); printf( diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 72ff745..14ccaa9 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -168,6 +168,18 @@ return ret; } +void print_supported_architectures(void) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(arch_names); i++) { + printf(i == 0? " ":", "); + printf("%s", arch_names[i].name); + } + + printf("\n"); +} + void print_supported_filetypes(void) { int i, number = ARRAY_SIZE(filetypes); diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 85dfdeb..8bae63e 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -204,6 +204,7 @@ int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output, uint32_t *location, const char *ignore_section); +void print_supported_architectures(void); void print_supported_filetypes(void); /* lzma/lzma.c */ -- To view, visit https://review.coreboot.org/25590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662 Gerrit-Change-Number: 25590 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: util/cbfstool: Print types on stdout
by Jonathan Neuschäfer (Code Review) 10 Apr '18

10 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25589 Change subject: util/cbfstool: Print types on stdout ...................................................................... util/cbfstool: Print types on stdout Currently, "cbfstool -h | less" doesn't show any file types under "TYPEs:". That's because the file types are printed with print_supported_filetypes, which uses LOG, which prints to stderr. Use printf print_supported_filetypes, and thus print to stdout, to make the usage output more normal. Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M util/cbfstool/common.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25589/1 diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 5a47c2f..72ff745 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -173,9 +173,9 @@ int i, number = ARRAY_SIZE(filetypes); for (i=0; i<number; i++) { - LOG(" %s%c", filetypes[i].name, (i==(number-1))?'\n':','); + printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':','); if ((i%8) == 7) - LOG("\n"); + printf("\n"); } } -- To view, visit https://review.coreboot.org/25589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99 Gerrit-Change-Number: 25589 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25588 ) Change subject: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG) ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24122/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69835/ : SUCCESS -- To view, visit https://review.coreboot.org/25588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Gerrit-Change-Number: 25588 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 12:58:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/fizz: Add device index for 2nd LAN
by Marco Chen (Code Review) 10 Apr '18

10 Apr '18

Marco Chen has posted comments on this change. ( https://review.coreboot.org/25587 ) Change subject: mb/google/fizz: Add device index for 2nd LAN ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/25587/1/src/mainboard/google/fizz/devicetre… File src/mainboard/google/fizz/devicetree.cb: https://review.coreboot.org/#/c/25587/1/src/mainboard/google/fizz/devicetre… PS1, Line 376: register "device_index" = "1" For multiple LAN interfaces, as I know we should set device_index from 1 to 10. In case of Fizz, we should set these two interfaces's device_index to 1 and 2 so VPDs would be ethernet_mac0 and ethernet_mac1. Therefore line 354 should have device_index as 1 and here be 2? -- To view, visit https://review.coreboot.org/25587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Gerrit-Change-Number: 25587 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-Comment-Date: Tue, 10 Apr 2018 12:55:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
by Jonathan Neuschäfer (Code Review) 10 Apr '18

10 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25588 Change subject: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG) ...................................................................... src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG) Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/google/kahlee/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/25588/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 1eb18f1..641287c 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -39,7 +39,7 @@ /* Configure cr50 interrupt pin for use in polling tpm status */ if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { - const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW | + const uint32_t flags = GPIO_EDGE_TRIG | GPIO_ACTIVE_LOW | GPIO_INT_STATUS_EN; gpio_set_interrupt(H1_PCH_INT, flags); } diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 2c3555b..e1ae5dd 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -23,7 +23,7 @@ #include <soc/iomap.h> #include <types.h> -#define GPIO_EDGEL_TRIG (0 << 8) +#define GPIO_EDGE_TRIG (0 << 8) #define GPIO_LEVEL_TRIG (1 << 8) #define GPIO_TRIGGER_MASK (1 << 8) -- To view, visit https://review.coreboot.org/25588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Gerrit-Change-Number: 25588 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: mb/google/fizz: Add device index for 2nd LAN
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25587 ) Change subject: mb/google/fizz: Add device index for 2nd LAN ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24121/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69834/ : SUCCESS -- To view, visit https://review.coreboot.org/25587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Gerrit-Change-Number: 25587 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 12:31:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/fizz: Add device index for 2nd LAN
by David Wu (Code Review) 10 Apr '18

10 Apr '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/25587 Change subject: mb/google/fizz: Add device index for 2nd LAN ...................................................................... mb/google/fizz: Add device index for 2nd LAN Fix 2nd LAN can't inherit correct MAC from VPD setting. BUG=b:77836343 BRANCH=Fizz TEST=Program the mac address to VPD in shell vpd -s ethernet_mac0=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Signed-off-by: David Wu <david_wu(a)quantatw.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25587/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 9d120ea..b957bc6 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -373,6 +373,7 @@ device pci 1d.0 on # PCI Express Port 9 for 2nd LAN chip drivers/net register "customized_leds" = "0x0fa5" + register "device_index" = "1" device pci 00.0 on end end end # PCI Express Port 9 for BtoB -- To view, visit https://review.coreboot.org/25587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Gerrit-Change-Number: 25587 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com>

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Change in coreboot[master]: siemens/mc_apl1: Make DRAM configuration more flexible
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25586 ) Change subject: siemens/mc_apl1: Make DRAM configuration more flexible ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24120/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69833/ : SUCCESS -- To view, visit https://review.coreboot.org/25586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 Gerrit-Change-Number: 25586 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 11:11:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Make DRAM configuration more flexible
by Mario Scheithauer (Code Review) 10 Apr '18

10 Apr '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/25586 Change subject: siemens/mc_apl1: Make DRAM configuration more flexible ...................................................................... siemens/mc_apl1: Make DRAM configuration more flexible By storing the FSP-M DRAM configuration parameter in the hwinfo block, one becomes more flexible in case of a change of the DRAM type. The configuration data from hwinfo block is a one-to-one representation of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and ending before parameter 'Ch0_Bit_swizzling' (offset 0x88). Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/romstage.c 1 file changed, 27 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/25586/1 diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 3462c76..24d03b6 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <hwilib.h> +#include <lib.h> #include <string.h> #include <soc/romstage.h> #include <fsp/api.h> @@ -48,67 +51,34 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; + uint8_t spd[0x80]; size_t num; /* setup early gpio before memory */ pads = brd_early_gpio_table(&num); gpio_configure_pads(pads, num); - /* DRAM Config settings */ - memupd->FspmConfig.Package = 0x1; - memupd->FspmConfig.Profile = 0x19; - memupd->FspmConfig.MemoryDown = 0x5; - memupd->FspmConfig.DDR3LPageSize = 0x2; - memupd->FspmConfig.DDR3LASR = 0x0; - memupd->FspmConfig.ScramblerSupport = 0x0; - memupd->FspmConfig.ChannelHashMask = 0x0; - memupd->FspmConfig.SliceHashMask = 0x0; - memupd->FspmConfig.InterleavedMode = 0x0; - memupd->FspmConfig.ChannelsSlicesEnable = 0x0; - memupd->FspmConfig.MinRefRate2xEnable = 0x1; - memupd->FspmConfig.DualRankSupportEnable = 0x1; - memupd->FspmConfig.RmtMode = 0x0; - memupd->FspmConfig.MemorySizeLimit = 0x1000; - memupd->FspmConfig.LowMemoryMaxValue = 0x0; - memupd->FspmConfig.DisableFastBoot = 0x0; - memupd->FspmConfig.HighMemoryMaxValue = 0x0; - memupd->FspmConfig.DIMM0SPDAddress = 0x0; - memupd->FspmConfig.DIMM1SPDAddress = 0x0; - memupd->FspmConfig.Ch0_RankEnable = 0x1; - memupd->FspmConfig.Ch0_DeviceWidth = 0x1; - memupd->FspmConfig.Ch0_DramDensity = 0x0; - memupd->FspmConfig.Ch0_Option = 0x3; - memupd->FspmConfig.Ch0_OdtConfig = 0x1; - memupd->FspmConfig.Ch0_TristateClk1 = 0x0; - memupd->FspmConfig.Ch0_Mode2N = 0x0; - memupd->FspmConfig.Ch0_OdtLevels = 0x0; - memupd->FspmConfig.Ch1_RankEnable = 0x1; - memupd->FspmConfig.Ch1_DeviceWidth = 0x1; - memupd->FspmConfig.Ch1_DramDensity = 0x0; - memupd->FspmConfig.Ch1_Option = 0x3; - memupd->FspmConfig.Ch1_OdtConfig = 0x1; - memupd->FspmConfig.Ch1_TristateClk1 = 0x0; - memupd->FspmConfig.Ch1_Mode2N = 0x0; - memupd->FspmConfig.Ch1_OdtLevels = 0x0; - memupd->FspmConfig.Ch2_RankEnable = 0x0; - memupd->FspmConfig.Ch2_DeviceWidth = 0x1; - memupd->FspmConfig.Ch2_DramDensity = 0x0; - memupd->FspmConfig.Ch2_Option = 0x3; - memupd->FspmConfig.Ch2_OdtConfig = 0x0; - memupd->FspmConfig.Ch2_TristateClk1 = 0x0; - memupd->FspmConfig.Ch2_Mode2N = 0x0; - memupd->FspmConfig.Ch2_OdtLevels = 0x0; - memupd->FspmConfig.Ch3_RankEnable = 0x0; - memupd->FspmConfig.Ch3_DeviceWidth = 0x1; - memupd->FspmConfig.Ch3_DramDensity = 0x0; - memupd->FspmConfig.Ch3_Option = 0x3; - memupd->FspmConfig.Ch3_OdtConfig = 0x0; - memupd->FspmConfig.Ch3_TristateClk1 = 0x0; - memupd->FspmConfig.Ch3_Mode2N = 0x0; - memupd->FspmConfig.Ch3_OdtLevels = 0x0; - memupd->FspmConfig.RmtCheckRun = 0x3; - memupd->FspmConfig.MrcDataSaving = 0x0; - memupd->FspmConfig.MrcFastBoot = 0x1; + /* Get DRAM configuration data from hwinfo block. + * The configuration data from hwinfo block is a one-to-one + * representation of the FSPM_UPD data starting with parameter + * 'Package' (offset 0x4d) and ending before parameter + * 'Ch0_Bit_swizzling' (offset 0x88). + */ + if (hwilib_find_blocks("hwinfo.hex")) { + printk(BIOS_ERR, + "HWInfo not found, use default values for FSP-M.\n"); + return; + } + + if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) { + printk(BIOS_ERR, + "SPD not found in HWInfo, use defaults for FSP-M.\n"); + return; + } + + memcpy(&memupd->FspmConfig.Package, &spd, + (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)- + (&memupd->FspmConfig.Package))); memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, sizeof(Ch0_Bit_swizzling)); @@ -119,6 +89,7 @@ memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, sizeof(Ch3_Bit_swizzling)); - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; memupd->FspmConfig.MsgLevelMask = 0x0; + memupd->FspmConfig.MrcDataSaving = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x1; } -- To view, visit https://review.coreboot.org/25586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 Gerrit-Change-Number: 25586 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: siemens/mc_apl1: Fix for using IDT PMIC
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25585 ) Change subject: siemens/mc_apl1: Fix for using IDT PMIC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24119/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69832/ : SUCCESS -- To view, visit https://review.coreboot.org/25585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Gerrit-Change-Number: 25585 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 10:54:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018