coreboot-gerrit April 2018

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Change in coreboot[master]: nb/intel/i945: Use common SMM_TSEG code
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25595 Change subject: nb/intel/i945: Use common SMM_TSEG code ...................................................................... nb/intel/i945: Use common SMM_TSEG code Use the common SMM_TSEG code to relocate the smihandler to TSEG. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/model_f4x/Makefile.inc M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/southbridge/intel/i82801gx/Makefile.inc 13 files changed, 51 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/25595/1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..0cb47da 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -13,6 +13,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON + select HAS_NO_SMRR if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index cd753db..0703099 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name subdirs-y += ../common +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 10ebcc7..df1cbbb 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -11,3 +11,4 @@ select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select HAS_NO_SMRR diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 4321f2a..13e08f0 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name subdirs-y += ../common +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820..0c6da97 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,4 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select HAS_NO_SMRR diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index b73a25d..7367914 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_f3x_init.c +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b5..c1e0dfd 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -6,3 +6,4 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select HAS_NO_SMRR diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 9aeb107..2f11d7f 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_f4x_init.c +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 482f98a..dcf3fb5 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -28,6 +28,7 @@ select RELOCATABLE_RAMSTAGE select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select SMM_TSEG config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index cc5f087..100ac9a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -366,6 +366,7 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +uintptr_t smm_region_start(void); #endif /* __ACPI__ */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 37f94b1..94f7dac 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <arch/acpi.h> +#include <cpu/intel/smm/gen1/smi.h> #include "i945.h" static int get_pcie_bar(u32 *base) @@ -118,6 +119,43 @@ assign_resources(dev->link_list); } +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + ESMRAMC); + return decode_tseg_size(esmramc); +} + +u32 northbridge_get_tseg_base(void) +{ + return (u32) smm_region_start(); +} + +void northbridge_write_smram(u8 smram) +{ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); +} + +/* + * Really doesn't belong here but will go away with parallel mp init, + * so let it be here for a while... + */ +int cpu_get_apic_id_map(int *apic_id_map) +{ + unsigned int i; + + /* Logical processors (threads) per core */ + const struct cpuid_result cpuid1 = cpuid(1); + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + + /* TODO in parallel MP cpuid(1).ebx */ + for (i = 0; i < cores; i++) + apic_id_map[i] = i; + + return cores; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 5f3513a..aeace48 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -43,7 +43,7 @@ } } -static uintptr_t smm_region_start(void) +uintptr_t smm_region_start(void) { uintptr_t tom; diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index bb68d93..70abbe2 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -33,8 +33,10 @@ ramstage-y += reset.c ramstage-y += watchdog.c +ifneq ($(CONFIG_SMM_TSEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S +endif smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c early_lpc.c -- To view, visit https://review.coreboot.org/25595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Gerrit-Change-Number: 25595 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/i82801gx: Use common Intel SMM code
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25594 Change subject: sb/intel/i82801gx: Use common Intel SMM code ...................................................................... sb/intel/i82801gx: Use common Intel SMM code Untested Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/smi.c M src/southbridge/intel/i82801gx/smihandler.c 5 files changed, 18 insertions(+), 877 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25594/1 diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 4aa2812..d8292b7 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -58,8 +58,14 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#else #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 +#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ +#define USB4_STS (1 << 14) /* i82801gx only */ #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) #define BATLOW_STS (1 << 10) @@ -69,7 +75,11 @@ #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#define GPE0_EN 0x2c +#else #define GPE0_EN 0x28 +#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 9fd19ed..e2beacd 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -26,6 +26,7 @@ select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SMM if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index df744fc..e82f54d 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -46,7 +46,6 @@ #if !defined(__SIMPLE_DEVICE__) void i82801gx_enable(device_t dev); #endif -void gpi_route_interrupt(u8 gpi, u8 mode); #else void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 7355d11..d94862d 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -24,6 +24,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <string.h> +#include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" /* I945 */ @@ -39,253 +40,6 @@ */ static u16 pmbase = DEFAULT_PMBASE; -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_DEBUG, "PM1_STS: "); - if (pm1_sts & (1 << 15)) - printk(BIOS_DEBUG, "WAK "); - if (pm1_sts & (1 << 14)) - printk(BIOS_DEBUG, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) - printk(BIOS_DEBUG, "PRBTNOR "); - if (pm1_sts & (1 << 10)) - printk(BIOS_DEBUG, "RTC "); - if (pm1_sts & (1 << 8)) - printk(BIOS_DEBUG, "PWRBTN "); - if (pm1_sts & (1 << 5)) - printk(BIOS_DEBUG, "GBL "); - if (pm1_sts & (1 << 4)) - printk(BIOS_DEBUG, "BM "); - if (pm1_sts & (1 << 0)) - printk(BIOS_DEBUG, "TMROF "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) - printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) - printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) - printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) - printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) - printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) - printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) - printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) - printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) - printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) - printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) - printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) - printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) - printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) - printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) - printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) - printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) - printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) - printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) - printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) - printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i = 31; i >= 16; i--) { - if (gpe0_sts & (1 << i)) - printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) - printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) - printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) - printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) - printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) - printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) - printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) - printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) - printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) - printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) - printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) - printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) - printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) - printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) - printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear ALT_GP_SMI_STS - * @return ALT_GP_SMI_STS register - */ -static u16 reset_alt_gp_smi_status(void) -{ - u16 reg16; - - reg16 = inl(pmbase + ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg16, pmbase + ALT_GP_SMI_STS); - - return reg16; -} - -static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) -{ - int i; - printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i = 15; i >= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) - printk(BIOS_DEBUG, "GPI%d ", i); - } - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) - printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) - printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) - printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) - printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) - printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) - printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) - printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) - printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) - printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) - printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) - printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) - printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) - printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - extern uint8_t smm_relocation_start, smm_relocation_end; static void *default_smm_area = NULL; @@ -430,12 +184,3 @@ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* The GDT or coreboot table is going to live here. But a long time - * after we relocated the GNVS, so this is not troublesome. - */ - *(u32 *)0x500 = (u32)gnvs; - outb(0xea, 0xb2); -} diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 3f537c0..1b4a063 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <halt.h> #include <pc80/mc146818rtc.h> +#include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" /* I945 */ @@ -45,246 +46,10 @@ */ global_nvs_t *gnvs = (global_nvs_t *)0x0; -static void alt_gpi_mask(u16 clr, u16 set) +void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); - alt_gp &= ~clr; - alt_gp |= set; - outw(alt_gp, pmbase + ALT_GP_SMI_EN); -} - -static void gpe0_mask(u32 clr, u32 set) -{ - u32 gpe0 = inl(pmbase + GPE0_EN); - gpe0 &= ~clr; - gpe0 |= set; - outl(gpe0, pmbase + GPE0_EN); -} - -void gpi_route_interrupt(u8 gpi, u8 mode) -{ - u32 gpi_rout; - if (gpi >= 16) - return; - - alt_gpi_mask(1 << gpi, 0); - gpe0_mask(1 << (gpi+16), 0); - - gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); - gpi_rout &= ~(3 << (2 * gpi)); - gpi_rout |= ((mode & 3) << (2 * gpi)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); - - if (mode == GPI_IS_SCI) - gpe0_mask(0, 1 << (gpi+16)); - else if (mode == GPI_IS_SMI) - alt_gpi_mask(0, 1 << gpi); -} - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_SPEW, "PM1_STS: "); - if (pm1_sts & (1 << 15)) - printk(BIOS_SPEW, "WAK "); - if (pm1_sts & (1 << 14)) - printk(BIOS_SPEW, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) - printk(BIOS_SPEW, "PRBTNOR "); - if (pm1_sts & (1 << 10)) - printk(BIOS_SPEW, "RTC "); - if (pm1_sts & (1 << 8)) - printk(BIOS_SPEW, "PWRBTN "); - if (pm1_sts & (1 << 5)) - printk(BIOS_SPEW, "GBL "); - if (pm1_sts & (1 << 4)) - printk(BIOS_SPEW, "BM "); - if (pm1_sts & (1 << 0)) - printk(BIOS_SPEW, "TMROF "); - printk(BIOS_SPEW, "\n"); - int reg16 = inw(pmbase + PM1_EN); - printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) - printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) - printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) - printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) - printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) - printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) - printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) - printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) - printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) - printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) - printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) - printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) - printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) - printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) - printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) - printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) - printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) - printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) - printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) - printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) - printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i = 31; i >= 16; i--) { - if (gpe0_sts & (1 << i)) - printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) - printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) - printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) - printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) - printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) - printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) - printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) - printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) - printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) - printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) - printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) - printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) - printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) - printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) - printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) - printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) - printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) - printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) - printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) - printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) - printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) - printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) - printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) - printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) - printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) - printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) - printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) - printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); + gnvs = *(global_nvs_t **)0x500; + *smm_done = 1; } int southbridge_io_trap_handler(int smif) @@ -304,312 +69,7 @@ return 0; } -/** - * @brief Set the EOS bit - */ -void southbridge_smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -static void busmaster_disable_on_bus(int bus) -{ - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - pci_devfn_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } -} - - -static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) -{ - u8 reg8; - u32 reg32; - u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - - // save and recover RTC port values - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); - get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); - - /* First, disable further SMIs */ - reg8 = inb(pmbase + SMI_EN); - reg8 &= ~SLP_SMI_EN; - outb(reg8, pmbase + SMI_EN); - - /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = acpi_sleep_from_pm1(reg32); - - /* Next, do the deed. - */ - - switch (slp_typ) { - case ACPI_S0: - printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case ACPI_S1: - printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case ACPI_S3: - printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - /* Invalidate the cache before going to S3 */ - wbinvd(); - break; - case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - - outl(0, pmbase + GPE0_EN); - - /* Always set the flag in case CMOS was changed on runtime. For - * "KEEP", switch to "OFF" - KEEP is software emulated - */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) - reg8 &= ~1; - else - reg8 |= 1; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* also iterates over all bridges on bus 0 */ - busmaster_disable_on_bus(0); - break; - default: - printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; - } - -#if !IS_ENABLED(CONFIG_SMM_TSEG) - /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore - * will never be unlocked because the next outl will switch off the CPU. - * This might open a small race between the smi_release_lock() and the outl() - * for other SMI handlers. Not sure if this could cause trouble. */ - if (slp_typ == ACPI_S3) - smi_release_lock(); -#endif - - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. - */ - outl(reg32 | SLP_EN, pmbase + PM1_CNT); - - /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ >= ACPI_S3) - halt(); - /* In most sleep states, the code flow of this function ends at - * the line above. However, if we entered sleep state S1 and wake - * up again, we will continue to execute code in this function. - */ - reg32 = inl(pmbase + PM1_CNT); - if (reg32 & SCI_EN) { - /* The OS is not an ACPI OS, so we set the state to S0 */ - reg32 &= ~(SLP_EN | SLP_TYP); - outl(reg32, pmbase + PM1_CNT); - } -} - -static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 pmctrl; - u8 reg8; - - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); - if (mainboard_smi_apmc(reg8)) - return; - - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - gnvs = *(global_nvs_t **)0x500; - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting up structures to %p\n", gnvs); - break; - default: - printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8); - } -} - -static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) -{ - u16 pm1_sts; - volatile u8 cmos_status; - - pm1_sts = reset_pm1_status(); - dump_pm1_status(pm1_sts); - - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ - if (pm1_sts & PWRBTN_STS) { - // power button pressed - u32 reg32; - reg32 = (7 << 10) | (1 << 13); - outl(reg32, pmbase + PM1_CNT); - } - - if (pm1_sts & RTC_STS) { - /* read RTC status register to disable the interrupt */ - cmos_status = cmos_read(RTC_REG_C); - printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status); - } -} - -static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 gpe0_sts; - - gpe0_sts = reset_gpe0_status(); - dump_gpe0_status(gpe0_sts); -} - -static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) -{ - u16 reg16; - reg16 = inw(pmbase + ALT_GP_SMI_STS); - outw(reg16, pmbase + ALT_GP_SMI_STS); - - reg16 &= inw(pmbase + ALT_GP_SMI_EN); - - mainboard_smi_gpi(reg16); - - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); -} - -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & MCSMI_EN) == 0) - return; - - printk(BIOS_DEBUG, "Microcontroller SMI.\n"); -} - - - -static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 tco_sts; - - tco_sts = reset_tco_status(); - - /* Any TCO event? */ - if (!tco_sts) - return; - - if (tco_sts & (1 << 8)) { - /* BIOSWR */ - u8 bios_cntl; - - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); - - if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - */ - - /* This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); - } /* No else for now? */ - } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ - /* Handle TCO timeout */ - printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else if (!tco_sts) { - dump_tco_status(tco_sts); - } -} - -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -654,80 +114,6 @@ #undef IOTRAP } -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); - -smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - southbridge_smi_gpi, // [10] GPI_STS - southbridge_smi_mc, // [11] MCSMI_STS - NULL, // [12] DEVMON_STS - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - southbridge_smi_monitor, // [21] MONITOR_STS - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] EL_SMI_STS - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] reserved - NULL, // [29] reserved - NULL, // [30] reserved - NULL // [31] reserved -}; - -/** - * @brief Interrupt handler for SMI# - * @param node - * @param state_save - */ - -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_finalize_all(void) { - int i, dump = 0; - u32 smi_sts; - - /* Update global variable pmbase */ - pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = reset_smi_status(); - - /* Filter all non-enabled SMI events */ - // FIXME Double check, this clears MONITOR - // smi_sts &= inl(pmbase + SMI_EN); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 31; i++) { - if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) - southbridge_smi[i](node, state_save); - else { - printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " - "handler available.\n", i); - dump = 1; - } - } - } - - if (dump) - dump_smi_status(smi_sts); } -- To view, visit https://review.coreboot.org/25594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Gerrit-Change-Number: 25594 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/pineview: Enable and allocate 8M for TSEG
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25593 Change subject: nb/intel/pineview: Enable and allocate 8M for TSEG ...................................................................... nb/intel/pineview: Enable and allocate 8M for TSEG TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/25593/1 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index a2cda84..9873d4d 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -62,7 +62,7 @@ #define REMAPBASE 0x98 #define REMAPLIMIT 0x9a #define SMRAM 0x9d /* System Management RAM Control */ -#define ESMRAM 0x9e /* Extended System Management RAM Control */ +#define ESMRAMC 0x9e /* Extended System Management RAM Control */ #define TOM 0xa0 #define TOUUD 0xa2 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 1f03820..98addb1 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -2040,7 +2040,7 @@ gttsize = ggc_to_gtt[(ggc & 0x300) >> 8]; tom = s->channel_capacity[0]; - tsegsize = 0x1; // 1MB + tsegsize = 0x8; // 1MB mmiosize = 0x400; // 1GB reclaim = false; @@ -2075,6 +2075,11 @@ pci_write_config32(PCI_DEV(0,0,0), BGSM, gttbase << 20); pci_write_config32(PCI_DEV(0,0,0), TSEG, tsegbase << 20); + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n", pci_read_config32(PCI_DEV(0,0,0), GBSM), gfxbase << 20); printk(BIOS_DEBUG, "BGSM (gtt) = verified %08x (written %08x)\n", -- To view, visit https://review.coreboot.org/25593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Gerrit-Change-Number: 25593 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/i945: Enable and allocate 8M for TSEG
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25592 Change subject: nb/intel/i945: Enable and allocate 8M for TSEG ...................................................................... nb/intel/i945: Enable and allocate 8M for TSEG TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/25592/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index bf486a0..7de2c73 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -192,6 +192,11 @@ gfxsize = 2; pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); -- To view, visit https://review.coreboot.org/25592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Gerrit-Change-Number: 25592 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25588 ) Change subject: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG) ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24125/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69838/ : SUCCESS -- To view, visit https://review.coreboot.org/25588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Gerrit-Change-Number: 25588 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 13:19:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Capitalize MB part name
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25591 ) Change subject: mb/google/octopus: Capitalize MB part name ...................................................................... Patch Set 1: Verified+1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/24126/ : SUCCESS -- To view, visit https://review.coreboot.org/25591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Gerrit-Change-Number: 25591 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 13:11:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/cbfstool: Print all supported architectures
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25590 ) Change subject: util/cbfstool: Print all supported architectures ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24124/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69837/ : SUCCESS -- To view, visit https://review.coreboot.org/25590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662 Gerrit-Change-Number: 25590 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 13:11:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/cbfstool: Print types on stdout
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25589 ) Change subject: util/cbfstool: Print types on stdout ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24123/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69836/ : SUCCESS -- To view, visit https://review.coreboot.org/25589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99 Gerrit-Change-Number: 25589 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 13:10:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Capitalize MB part name
by Justin TerAvest (Code Review) 10 Apr '18

10 Apr '18

Justin TerAvest has uploaded a new patch set (#2). ( https://review.coreboot.org/25591 ) Change subject: mb/google/octopus: Capitalize MB part name ...................................................................... mb/google/octopus: Capitalize MB part name This is for consistency with other platforms. BUG=b:77494826 BRANCH=None TEST=Sucessfully rebooted, saw updated name in SMBIOS Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/25591/2 -- To view, visit https://review.coreboot.org/25591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Gerrit-Change-Number: 25591 Gerrit-PatchSet: 2 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: mb/google/octopus: Capitalize MB part name
by Justin TerAvest (Code Review) 10 Apr '18

10 Apr '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25591 Change subject: mb/google/octopus: Capitalize MB part name ...................................................................... mb/google/octopus: Capitalize MB part name This is for consistency with other platforms. BUG=b:77494826 Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/25591/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 60c98c0..815f664 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -45,8 +45,8 @@ config MAINBOARD_PART_NUMBER string - default "yorp" if BOARD_GOOGLE_YORP - default "bip" if BOARD_GOOGLE_BIP + default "Yorp" if BOARD_GOOGLE_YORP + default "Bip" if BOARD_GOOGLE_BIP default "octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY -- To view, visit https://review.coreboot.org/25591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Gerrit-Change-Number: 25591 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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coreboot-gerrit April 2018