coreboot-gerrit April 2018

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Change in coreboot[master]: Documentation: Fix a bunch of typos
by Patrick Georgi (Code Review) 10 Apr '18

10 Apr '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/25571 ) Change subject: Documentation: Fix a bunch of typos ...................................................................... Documentation: Fix a bunch of typos Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/25571 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/Intel/NativeRaminit/SandyBridge_registers.md M Documentation/Lesson2.md M Documentation/RFC/chip.tex M Documentation/cbfs.txt M Documentation/corebootBuildingGuide.tex 5 files changed, 11 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md index 2dce11b..c961890 100644 --- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md +++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md @@ -966,7 +966,7 @@ *Width:* 24 Bit -*Desc:* TC_DBP - Timming of DDR - Bin Parameter Register, Channel 0 +*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0 |Bit| Description | |---|-------------| diff --git a/Documentation/Lesson2.md b/Documentation/Lesson2.md index 0263ced..ec929c8 100644 --- a/Documentation/Lesson2.md +++ b/Documentation/Lesson2.md @@ -20,7 +20,7 @@ <https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/us…)> and follow the instructions there. Then, skip to Part 3. -Additonally, that section of the Web site provides explanation on starting +Additionally, that section of the Web site provides explanation on starting an ssh-agent, which may be particularly helpful for those who anticipate frequently uploading changes. @@ -110,7 +110,7 @@ git commit -s -**Note:** The -s adds a signed-off-by line by the commiter. Your commit should be +**Note:** The -s adds a signed-off-by line by the committer. Your commit should be signed off with your name and email (i.e. **Your Name** **<Your Email>**, based on what you set with git config earlier). @@ -236,7 +236,7 @@ git clone https://github.com/magicmonty/bash-git-prompt.git .bash-git-prompt --depth=1 **Note:** cd will change your directory to your home directory, so the -git clone commmand will be run there. +git clone command will be run there. Finally, open the ~/.bashrc file and append the following two lines: diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex index 5e366b8..01f40c1 100644 --- a/Documentation/RFC/chip.tex +++ b/Documentation/RFC/chip.tex @@ -14,7 +14,7 @@ \section{Goals} The goals of the new chip architecture are these: \begin{itemize} -\item seperate implementation details from specification in the Config file +\item separate implementation details from specification in the Config file (translation: no more C code in Config files) \item make the specification easier for people to use and understand \item remove private details of a given chip to the chip file as much @@ -223,7 +223,7 @@ const char *value; }; -These get filled in by the config tool as before. The linuxbios libary can +These get filled in by the config tool as before. The linuxbios library can then provide a generic parsing function for the superios to use. The remaining question is how should the superio command look in diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 6c5c228..7adae61 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -36,7 +36,7 @@ The header on each "file" (or component, as I like to style them) has been simplified - We now only store the length, the type, the checksum, and the offset to the data. The name scheme remains the same. The -addtional information, which is component specific, has been moved to +additional information, which is component specific, has been moved to the component itself (see below). The components are arranged in the ROM aligned along the specified @@ -245,7 +245,7 @@ | ... | \--------/ <- start + 'offset' + 'len' -== Searching Alogrithm == +== Searching Algorithm == To locate a specific component in the ROM, one starts at the 'offset' specified in the CBFS master header. For this example, the offset will @@ -379,7 +379,7 @@ PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data -PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment +PAYLOAD_SEGMENT_BSS 0x20535342 The memory specified by the segment should be zeroed PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for the payload diff --git a/Documentation/corebootBuildingGuide.tex b/Documentation/corebootBuildingGuide.tex index 867891b..e451ad4 100644 --- a/Documentation/corebootBuildingGuide.tex +++ b/Documentation/corebootBuildingGuide.tex @@ -413,8 +413,8 @@ \end{verbatim} } -% Does anyone have a better word to describe the phylosophy of spliting changes to patches? -You need to realize that the changes you have made should be well devided into +% Does anyone have a better word to describe the philosophy of splitting changes to patches? +You need to realize that the changes you have made should be well divided into several commits. Each of them has one and only one meaning. You could use git rebase -i to split, squash, remove, rewrite you comment. -- To view, visit https://review.coreboot.org/25571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Gerrit-Change-Number: 25571 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation: Fix a bunch of typos
by Patrick Georgi (Code Review) 10 Apr '18

10 Apr '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/25571 ) Change subject: Documentation: Fix a bunch of typos ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/25571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Gerrit-Change-Number: 25571 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 10:50:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block/cpu: Fix cpu_get_power_max
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25584 ) Change subject: soc/intel/common/block/cpu: Fix cpu_get_power_max ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24118/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69831/ : SUCCESS -- To view, visit https://review.coreboot.org/25584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3 Gerrit-Change-Number: 25584 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 10:47:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Fix for using IDT PMIC
by Mario Scheithauer (Code Review) 10 Apr '18

10 Apr '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/25585 Change subject: siemens/mc_apl1: Fix for using IDT PMIC ...................................................................... siemens/mc_apl1: Fix for using IDT PMIC Due to an accuracy issue on IMON in the IDT PMIC, the reported system power consumption was higher than the actual consumption. To prevent this problem, a logic must be implement in mainboard_init(). This logic consists of slope and offset as constants for Vcc and Vnn, which needs to be programmed by coreboot. This fix compensates for the accuracy issue. Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c 1 file changed, 80 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/25585/1 diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index fd19cd1..81e215b 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -15,14 +15,17 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <gpio.h> #include <hwilib.h> #include <i210.h> +#include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <string.h> @@ -35,6 +38,9 @@ #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 +#define BIOS_MAILBOX_DATA 0x7080 +#define BIOS_MAILBOX_INTERFACE 0x7084 + /** \brief This function can decide if a given MAC address is valid or not. * Currently, addresses filled with 0xff or 0x00 are not valid. * @param mac Buffer to the MAC address to check @@ -114,9 +120,82 @@ { const struct pad_config *pads; size_t num; + uint16_t stall_count; + uint32_t power_max, data; pads = brd_gpio_table(&num); gpio_configure_pads(pads, num); + + printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - Start\n"); + + /* Calculate CPU TDP in mW */ + power_max = cpu_get_power_max(); + printk(BIOS_DEBUG, "PMIC: CPU TDP %d mW.\n", power_max); + + /* + * Fix Vnn slope and offset value. + * slope = 0x4a4 # 2.32 + * offset = 0xfa0d # -2.975 + */ + stall_count = 0; + while (stall_count < 1000) { + /* Read P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR */ + data = MCHBAR32(BIOS_MAILBOX_INTERFACE); + /* Check RUN_BUSY bit. */ + if ((data & (1 << 31)) == (1 << 31)) + mdelay(1); + else + break; + stall_count++; + } + if (stall_count == 1000) { + printk(BIOS_ERR, + "PMIC: Cannot set Vnn slope and offset value.\n"); + } else { + /* Set Vnn values into P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR. */ + MCHBAR32(BIOS_MAILBOX_DATA) = 0xfa0d04a4; + /* Set command, address and busy bit. */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000011d; + printk(BIOS_DEBUG, "PMIC: Fix Vnn slope and offset value.\n"); + } + + /* + * Fix Vcc slope and offset value. + * Premium and High SKU: + * slope = 0x466 # 2.2 + * offset = 0xe833 # -11.9 + * Low and Intermediate SKU: + * slope = 0x3b3 # 1.85 + * offset = 0xed33 # -9.4 + */ + stall_count = 0; + while (stall_count < 1000) { + data = MCHBAR32(BIOS_MAILBOX_INTERFACE); + if ((data & (1 << 31)) == (1 << 31)) + mdelay(1); + else + break; + stall_count++; + } + if (stall_count == 1000) { + printk(BIOS_ERR, + "PMIC: Cannot set Vcc slope and offset value.\n"); + } else { + /* + * CPU TDP limit between Premium/High and Low/Intermediate SKU + * is 9010 mW. + */ + if (power_max > 9010) { + MCHBAR32(BIOS_MAILBOX_DATA) = 0xe8330466; + MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000001d; + printk(BIOS_DEBUG, "PMIC: Fix Vcc for Premium SKU.\n"); + } else { + MCHBAR32(BIOS_MAILBOX_DATA) = 0xed3303b3; + MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000001d; + printk(BIOS_DEBUG, "PMIC: Fix Vcc for Low SKU.\n"); + } + } + printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - End\n"); } static void mainboard_final(void *chip_info) @@ -125,7 +204,7 @@ uint16_t cmd = 0; device_t dev = NULL; - /** + /* * Set up the DP2LVDS converter. * ptn3460_init() may only be executed after i2c bus init. */ -- To view, visit https://review.coreboot.org/25585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Gerrit-Change-Number: 25585 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: soc/intel/common/block/cpu: Fix cpu_get_power_max
by Mario Scheithauer (Code Review) 10 Apr '18

10 Apr '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/25584 Change subject: soc/intel/common/block/cpu: Fix cpu_get_power_max ...................................................................... soc/intel/common/block/cpu: Fix cpu_get_power_max To avoid rounding errors with the current data types, the formula in this function must be converted. Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/25584/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index ed1ba0f..0b1599a 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -287,7 +287,7 @@ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); power_unit = 2 << ((msr.lo & 0xf) - 1); msr = rdmsr(MSR_PKG_POWER_SKU); - return ((msr.lo & 0x7fff) / power_unit) * 1000; + return (msr.lo & 0x7fff) * 1000 / power_unit; } uint32_t cpu_get_max_turbo_ratio(void) -- To view, visit https://review.coreboot.org/25584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3 Gerrit-Change-Number: 25584 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: lib/memrange: Introduce method to clone memrange
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25582 ) Change subject: lib/memrange: Introduce method to clone memrange ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24115/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69828/ : SUCCESS -- To view, visit https://review.coreboot.org/25582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I64b27bf2611ca310385ef680f030a3e4aa0c2680 Gerrit-Change-Number: 25582 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 09:27:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: lib/bootmem: Add method to walk memory tables
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25583 ) Change subject: lib/bootmem: Add method to walk memory tables ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24116/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69829/ : SUCCESS -- To view, visit https://review.coreboot.org/25583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926 Gerrit-Change-Number: 25583 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 09:24:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/lib: Add uImage support
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25019 ) Change subject: src/lib: Add uImage support ...................................................................... Patch Set 17: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24117/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69830/ : SUCCESS -- To view, visit https://review.coreboot.org/25019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Gerrit-Change-Number: 25019 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 09:23:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: lib/bootmem: Introduce new memory type
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25383 ) Change subject: lib/bootmem: Introduce new memory type ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24114/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69827/ : SUCCESS -- To view, visit https://review.coreboot.org/25383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Gerrit-Change-Number: 25383 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 09:20:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: lib: Add flattened devicetree support
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25523 ) Change subject: lib: Add flattened devicetree support ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24113/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69826/ : SUCCESS -- To view, visit https://review.coreboot.org/25523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a Gerrit-Change-Number: 25523 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Tue, 10 Apr 2018 09:19:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018