coreboot-gerrit March 2018

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Change in coreboot[master]: [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common
by Ravishankar Sarawadi (Code Review) 09 Mar '18

09 Mar '18

Hello Subrata Banik, build bot (Jenkins), Lijian Zhao, Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/25087 to look at the new patch set (#2). Change subject: [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common ...................................................................... [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common Move SPI to GSPI bus and devfn mapping to GSPI common code. BUG=None BRANCH=None TEST=Build coreboot and do BAT test for SKL, CNL platform. Change-Id: I175ca6eab369276c693c78acc4d8ac9cd49ad152 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/cannonlake/gspi.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/skylake/gspi.c 3 files changed, 32 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25087/2 -- To view, visit https://review.coreboot.org/25087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I175ca6eab369276c693c78acc4d8ac9cd49ad152 Gerrit-Change-Number: 25087 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25087 ) Change subject: [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22852/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68430/ : SUCCESS -- To view, visit https://review.coreboot.org/25087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I175ca6eab369276c693c78acc4d8ac9cd49ad152 Gerrit-Change-Number: 25087 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Mar 2018 00:56:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common
by Ravishankar Sarawadi (Code Review) 09 Mar '18

09 Mar '18

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/25087 Change subject: [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common ...................................................................... [WIP]soc/intel/common/block/gspi: move SPI to GSPI mapping to common Move SPI to GSPI bus and devfn mapping to GSPI common code. BUG=None BRANCH=None TEST=Build coreboot and do BAT test for SKL, CNL platform. Change-Id: I175ca6eab369276c693c78acc4d8ac9cd49ad152 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/cannonlake/gspi.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/skylake/gspi.c 3 files changed, 30 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25087/1 diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index e4f682d..945c8c8 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -43,30 +43,3 @@ { return EARLY_GSPI_BASE_ADDRESS; } - -/* - * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust - * the bus # accordingly when referring to SPI / GSPI bus numbers. - */ -#define GSPI_TO_SPI_BUS(x) ((x) + 1) -#define SPI_TO_GSPI_BUS(x) ((x) - 1) - -int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus) -{ - if (spi_bus == 0) - return -1; - - *gspi_bus = SPI_TO_GSPI_BUS(spi_bus); - if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) - return -1; - - return 0; -} - -int gspi_soc_bus_to_devfn(unsigned int gspi_bus) -{ - if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) - return -1; - - return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus)); -} diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 60c7391..db68a2b 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <intelblocks/gspi.h> +#include <intelblocks/spi.h> #include <string.h> #include <timer.h> @@ -172,6 +173,35 @@ #endif +/* + * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust + * the bus # accordingly when referring to SPI / GSPI bus numbers. + */ +#define GSPI_TO_SPI_BUS(x) ((x) + 1) +#define SPI_TO_GSPI_BUS(x) ((x) - 1) + +__attribute__((weak)) int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, + unsigned int *gspi_bus) +{ + if (spi_bus == 0) + return -1; + + if (SPI_TO_GSPI_BUS(spi_bus) >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + *gspi_bus = SPI_TO_GSPI_BUS(spi_bus); + + return 0; +} + +__attribute__((weak)) int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus)); +} + static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus) { uintptr_t bus_base, gspi_base_addr; diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c index 252be777..393763d 100644 --- a/src/soc/intel/skylake/gspi.c +++ b/src/soc/intel/skylake/gspi.c @@ -42,30 +42,3 @@ { return EARLY_GSPI_BASE_ADDRESS; } - -/* - * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust - * the bus # accordingly when referring to SPI / GSPI bus numbers. - */ -#define GSPI_TO_SPI_BUS(x) (x + 1) -#define SPI_TO_GSPI_BUS(x) (x - 1) - -int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus) -{ - if (spi_bus == 0) - return -1; - - *gspi_bus = SPI_TO_GSPI_BUS(spi_bus); - if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) - return -1; - - return 0; -} - -int gspi_soc_bus_to_devfn(unsigned int gspi_bus) -{ - if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) - return -1; - - return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus)); -} -- To view, visit https://review.coreboot.org/25087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I175ca6eab369276c693c78acc4d8ac9cd49ad152 Gerrit-Change-Number: 25087 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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Change in coreboot[master]: meowth: Add SAR Sensor in devicetree
by Furquan Shaikh (Code Review) 09 Mar '18

09 Mar '18

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/25062 ) Change subject: meowth: Add SAR Sensor in devicetree ...................................................................... meowth: Add SAR Sensor in devicetree Add left and right semtech SAR sensor. BUG=b:74363445 TEST=Test on meowth, alongside 24962. Check in sysfs that SX9310 is presented: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:09/SX9310:00 /sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:0d/SX9310:01 Change-Id: I017db1105800003b312e75dc7e1e27be535a457a Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://review.coreboot.org/25062 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/zoombini/variants/meowth/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/gpio.c 2 files changed, 26 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 4250121..2d15c97 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -95,7 +95,17 @@ device i2c 0a on end end end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""SX9310"" + register "name" = ""SEMTECH SX9310"" + register "desc" = ""Left SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C3_IRQ)" + register "speed" = "I2C_SPEED_FAST_PLUS" + register "uid" = "1" + device i2c 28 on end + end + end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on chip drivers/i2c/max98373 @@ -123,7 +133,17 @@ device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 - device pci 19.1 on end # I2C #5 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""SX9310"" + register "name" = ""SEMTECH SX9310"" + register "desc" = ""Right SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C4_IRQ)" + register "speed" = "I2C_SPEED_FAST_PLUS" + register "uid" = "0" + device i2c 28 on end + end + end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index 78cab5a..507e653 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -86,8 +86,10 @@ /* SMBCLK */ PAD_NC(GPP_C0, NONE), /* SMBDATA */ PAD_NC(GPP_C1, NONE), /* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP), /* GPP_C2_STRAP */ -/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* PCH_SAR1_INT_L */ -/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* PCH_SAR0_INT_L */ +/* SML0CLK */ PAD_CFG_GPI_APIC(GPP_C3, NONE, DEEP, LEVEL, + NONE), /* PCH_SAR1_INT_L */ +/* SML0DATA */ PAD_CFG_GPI_APIC(GPP_C4, NONE, DEEP, LEVEL, + NONE), /* PCH_SAR0_INT_L */ /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */ /* SM1CLK */ PAD_CFG_GPO(GPP_C6, 1, DEEP), /* PCH_SAR_PWR_EN */ /* SM1DATA */ PAD_NC(GPP_C7, NONE), -- To view, visit https://review.coreboot.org/25062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I017db1105800003b312e75dc7e1e27be535a457a Gerrit-Change-Number: 25062 Gerrit-PatchSet: 5 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: meowth: Add SAR Sensor in devicetree
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25062 ) Change subject: meowth: Add SAR Sensor in devicetree ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22851/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68429/ : SUCCESS -- To view, visit https://review.coreboot.org/25062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I017db1105800003b312e75dc7e1e27be535a457a Gerrit-Change-Number: 25062 Gerrit-PatchSet: 4 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 23:36:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22850/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68428/ : SUCCESS -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 5 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 09 Mar 2018 22:43:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68427/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22849/ : SUCCESS -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 09 Mar 2018 22:35:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22848/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/68426/ : ABORTED -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 09 Mar 2018 22:32:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add support for GSPI
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24906 ) Change subject: soc/intel/apollolake: Add support for GSPI ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22847/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68425/ : SUCCESS -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 22:18:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common: Enable decoding of the COMB range to LPC based on K...
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25045 ) Change subject: soc/intel/common: Enable decoding of the COMB range to LPC based on Kconfig ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68424/ : SUCCESS -- To view, visit https://review.coreboot.org/25045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc Gerrit-Change-Number: 25045 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 09 Mar 2018 22:02:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit March 2018