coreboot-gerrit March 2018

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Change in coreboot[master]: mainboard/opencellular/rotundu: Fix vboot and TPM support
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25084 ) Change subject: mainboard/opencellular/rotundu: Fix vboot and TPM support ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68414/ : SUCCESS -- To view, visit https://review.coreboot.org/25084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Gerrit-Change-Number: 25084 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 17:19:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBNV CMOS support
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25085 ) Change subject: soc/intel/fsp_baytrail: Add VBNV CMOS support ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22838/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68415/ : SUCCESS -- To view, visit https://review.coreboot.org/25085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c1075f8e579c546edb4ff0581764a6a6aa7e89a Gerrit-Change-Number: 25085 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 17:15:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/opencellular/rotundu: Fix vboot and TPM support
by Philipp Deppenwiese (Code Review) 09 Mar '18

09 Mar '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25084 to look at the new patch set (#2). Change subject: mainboard/opencellular/rotundu: Fix vboot and TPM support ...................................................................... mainboard/opencellular/rotundu: Fix vboot and TPM support * Remove TPM setup in mainboard entry. * Fix kconfig selects. * Add 8M and 16M flashmaps for vboot support. Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/mainboard/opencellular/rotundu/Kconfig M src/mainboard/opencellular/rotundu/mainboard.c A src/mainboard/opencellular/rotundu/vboot-16M.fmd A src/mainboard/opencellular/rotundu/vboot-8M.fmd 4 files changed, 81 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/25084/2 -- To view, visit https://review.coreboot.org/25084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Gerrit-Change-Number: 25084 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBNV CMOS support
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25085 ) Change subject: soc/intel/fsp_baytrail: Add VBNV CMOS support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22837/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68413/ : SUCCESS -- To view, visit https://review.coreboot.org/25085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c1075f8e579c546edb4ff0581764a6a6aa7e89a Gerrit-Change-Number: 25085 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 17:09:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBNV CMOS support
by Philipp Deppenwiese (Code Review) 09 Mar '18

09 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/25085 Change subject: soc/intel/fsp_baytrail: Add VBNV CMOS support ...................................................................... soc/intel/fsp_baytrail: Add VBNV CMOS support * Add VBNV CMOS fsp_baytrail SoC support. * Add VBOOT_VBNV_CMOS to opencellular rotundu. Change-Id: I2c1075f8e579c546edb4ff0581764a6a6aa7e89a Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/mainboard/opencellular/rotundu/Kconfig M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/pmutil.c 4 files changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/25085/1 diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index 79b67fb..65c43d0 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -34,6 +34,7 @@ config VBOOT select MRC_CACHE_FMAP + select VBOOT_VBNV_CMOS select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index e01a944..0cf99de 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c +romstage-y += pmutil.c ramstage-y += pmutil.c ramstage-y += southcluster.c romstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 9bafdc2..16705cf 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -290,6 +290,9 @@ static inline void southcluster_log_state(void) {} #endif +/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); + #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ #endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index a588412..ee99917 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -15,18 +15,20 @@ #include <stdint.h> #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pmc.h> +#include <security/vboot/vbnv.h> -#if defined(__SMM__) +#if defined(__SIMPLE_DEVICE__) -static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline pci_devfn_t get_pcu_dev(void) +static inline device_t get_pcu_dev(void) { return pcu_dev; } @@ -358,3 +360,27 @@ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); } + +int rtc_failure(void) +{ + uint32_t gen_pmcon1; + int rtc_fail; + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps != NULL) + gen_pmcon1 = ps->gen_pmcon1; + else + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + + rtc_fail = !!(gen_pmcon1 & RPS); + + if (rtc_fail) + printk(BIOS_DEBUG, "RTC failure.\n"); + + return rtc_fail; +} + +int vbnv_cmos_failed(void) +{ + return rtc_failure(); +} -- To view, visit https://review.coreboot.org/25085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c1075f8e579c546edb4ff0581764a6a6aa7e89a Gerrit-Change-Number: 25085 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: mainboard/opencellular/rotundu: Fix TPM and VBoot 2 support
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25084 ) Change subject: mainboard/opencellular/rotundu: Fix TPM and VBoot 2 support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22836/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68412/ : SUCCESS -- To view, visit https://review.coreboot.org/25084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Gerrit-Change-Number: 25084 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 16:56:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/fsp_baytrail: Fix vboot and TPM support
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23798 ) Change subject: soc/fsp_baytrail: Fix vboot and TPM support ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22835/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68411/ : SUCCESS -- To view, visit https://review.coreboot.org/23798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da Gerrit-Change-Number: 23798 Gerrit-PatchSet: 9 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 16:31:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/opencellular/rotundu: Fix TPM and VBoot 2 support
by Philipp Deppenwiese (Code Review) 09 Mar '18

09 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/25084 Change subject: mainboard/opencellular/rotundu: Fix TPM and VBoot 2 support ...................................................................... mainboard/opencellular/rotundu: Fix TPM and VBoot 2 support Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/mainboard/opencellular/rotundu/Kconfig M src/mainboard/opencellular/rotundu/mainboard.c A src/mainboard/opencellular/rotundu/vboot-16M.fmd A src/mainboard/opencellular/rotundu/vboot-8M.fmd 4 files changed, 81 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/25084/1 diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index 761a21d..79b67fb 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -28,10 +28,16 @@ select USE_BLOBS select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select MAINBOARD_HAS_LPC_TPM - select TPM1 + select MAINBOARD_HAS_TPM1 if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU +config VBOOT + select MRC_CACHE_FMAP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + config VARIANT_DIR string default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU @@ -67,6 +73,12 @@ hex default 0xfffb0000 +config FMDFILE + string + depends on VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-8M.fmd" if BOARD_ROMSIZE_KB_8192 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-16M.fmd" + # FIXME: Slow boot performance when increasing CBFS_SIZE beyond 8MB? config CBFS_SIZE hex diff --git a/src/mainboard/opencellular/rotundu/mainboard.c b/src/mainboard/opencellular/rotundu/mainboard.c index dbcfe2d..cabef0d 100644 --- a/src/mainboard/opencellular/rotundu/mainboard.c +++ b/src/mainboard/opencellular/rotundu/mainboard.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <arch/acpi.h> -#include <security/tpm/tspi.h> /* * mainboard_enable is executed as first thing after enumerate_buses(). @@ -26,12 +25,6 @@ */ static void mainboard_enable(device_t dev) { - if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) && - !IS_ENABLED(CONFIG_VBOOT)) { - int s3resume = acpi_is_wakeup_s3(); - - tpm_setup(s3resume); - } } /* diff --git a/src/mainboard/opencellular/rotundu/vboot-16M.fmd b/src/mainboard/opencellular/rotundu/vboot-16M.fmd new file mode 100644 index 0000000..778d537 --- /dev/null +++ b/src/mainboard/opencellular/rotundu/vboot-16M.fmd @@ -0,0 +1,37 @@ +FLASH 16M { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0xd00000 { + RW_SECTION_A@0x0 0x410040 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x400000 + RW_FWID_A@0x410000 0x40 + } + RW_SECTION_B@0x410040 0x410040 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x400000 + RW_FWID_B@0x410000 0x40 + } + RW_MRC_CACHE@0x820080 0x10000 + RW_ELOG@0x830080 0x4000 + RW_SHARED@0x834080 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x838080 0x2000 + UNUSED_HOLE@0x83A080 0x2C5F80 + WP_RO@0xB00000 0x500000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x2f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x400000 + } + } + } +} diff --git a/src/mainboard/opencellular/rotundu/vboot-8M.fmd b/src/mainboard/opencellular/rotundu/vboot-8M.fmd new file mode 100644 index 0000000..ea0c86a --- /dev/null +++ b/src/mainboard/opencellular/rotundu/vboot-8M.fmd @@ -0,0 +1,31 @@ +FLASH 8M { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0x500000 { + RW_SECTION_A@0x0 0x1e6000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x1d5fc0 + RW_FWID_A@0x1e5fc0 0x40 + } + RW_MRC_CACHE@0x1e6000 0x10000 + RW_ELOG@0x1f6000 0x4000 + RW_SHARED@0x1fa000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1fe000 0x2000 + WP_RO@0x200000 0x300000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x2f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x200000 + } + } + } +} -- To view, visit https://review.coreboot.org/25084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Gerrit-Change-Number: 25084 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: soc/fsp_baytrail: Fix vboot and TPM support
by build bot (Jenkins) (Code Review) 09 Mar '18

09 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23798 ) Change subject: soc/fsp_baytrail: Fix vboot and TPM support ...................................................................... Patch Set 8: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22834/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/68410/ : ABORTED -- To view, visit https://review.coreboot.org/23798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da Gerrit-Change-Number: 23798 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 16:26:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]src/drivers/spi: Read Winbond's flash protection bits
by Furquan Shaikh (Code Review) 09 Mar '18

09 Mar '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/25082 ) Change subject: [WIP]src/drivers/spi: Read Winbond's flash protection bits ...................................................................... Patch Set 1: (10 comments) https://review.coreboot.org/#/c/25082/1/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c: https://review.coreboot.org/#/c/25082/1/src/drivers/spi/spi_flash.c@69 PS1, Line 69: printk(BIOS_WARNING, "SF: Failed to send command %02x: %d\n", : cmd[0], ret); Now that the command can contain more than one byte do you want to do something like this: if (ret) { printk(BIOS_WARNING, "SF: Failed to send command ret: %d, cmd:", ret); for (i = 0; i < cmd_len; i++) printk(BIOS_WARNING, "%02x ", cmd[i]); printk(BIOS_WARNING, "\n"); } https://review.coreboot.org/#/c/25082/1/src/drivers/spi/spi_flash.c@438 PS1, Line 438: ) || !region https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@199 PS1, Line 199: port part https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@204 PS1, Line 204: i size_t i https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@219 PS1, Line 219: 1 use a macro for this? https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@233 PS1, Line 233: port part https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@238 PS1, Line 238: block size_t? https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@266 PS1, Line 266: KiB Do you really need to divide by KiB? block = reg.s.sec ? (4 * KiB) : max(64 * KiB, flash->size / 64); https://review.coreboot.org/#/c/25082/1/src/drivers/spi/winbond.c@285 PS1, Line 285: 4 magic value. Do you want to add a macro for this? https://review.coreboot.org/#/c/25082/1/src/include/spi_flash.h File src/include/spi_flash.h: https://review.coreboot.org/#/c/25082/1/src/include/spi_flash.h@107 PS1, Line 107: 0 if the device doesn't support block protection : * 0 if the device doesn't enable block protection : * 0 Do you think it would help if we returned different return codes for these caes? -- To view, visit https://review.coreboot.org/25082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Gerrit-Change-Number: 25082 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 09 Mar 2018 15:51:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit March 2018