coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Disable RTC write protect
by build bot (Jenkins) (Code Review) 08 Mar '18

08 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25069 ) Change subject: soc/intel/cannonlake: Disable RTC write protect ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68401/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22826/ : SUCCESS -- To view, visit https://review.coreboot.org/25069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b Gerrit-Change-Number: 25069 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Vincent Palatin <vpalatin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 02:19:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/zoombini/variants/meowth: change gpios to no-connects
by Nick Vaccaro (Code Review) 08 Mar '18

08 Mar '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/25070 Change subject: mb/google/zoombini/variants/meowth: change gpios to no-connects ...................................................................... mb/google/zoombini/variants/meowth: change gpios to no-connects The following gpios are no longer needed and are now configured as no-connects : GPP_C6, GPP_H4, GPP_H5 BUG=b:74406599 BRANCH=master TEST=none Change-Id: I55769336195db0e57dfbaf5b5770e15050138341 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/zoombini/variants/meowth/gpio.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/25070/1 diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index 78cab5a..2455a0a 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -89,7 +89,7 @@ /* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* PCH_SAR1_INT_L */ /* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* PCH_SAR0_INT_L */ /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */ -/* SM1CLK */ PAD_CFG_GPO(GPP_C6, 1, DEEP), /* PCH_SAR_PWR_EN */ +/* SM1CLK */ PAD_NC(GPP_C6, NONE), /* SM1DATA */ PAD_NC(GPP_C7, NONE), /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART_PCH_RX_DEBUG_TX */ @@ -209,10 +209,8 @@ NF3), /* CNV_RF_RESET_L */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* WLAN_CLKREQ0 */ /* I2S2_RXD */ PAD_NC(GPP_H3, NONE), -/* I2C2_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, - NF1), /* PCH_BL_I2C2_SDA */ -/* I2C2_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, - NF1), /* PCH_BL_I2C2_SCL */ +/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* PCH_AUDIO_I2C3_SDA */ /* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, -- To view, visit https://review.coreboot.org/25070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I55769336195db0e57dfbaf5b5770e15050138341 Gerrit-Change-Number: 25070 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: soc/intel/cannonlake: Disable RTC write protect
by Caveh Jalali (Code Review) 08 Mar '18

08 Mar '18

Hello caveh jalali, I'd like you to do a code review. Please visit https://review.coreboot.org/25069 to review the following change. Change subject: soc/intel/cannonlake: Disable RTC write protect ...................................................................... soc/intel/cannonlake: Disable RTC write protect The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we need this memory to be writable. We normally over-ride this in the SoC chip init code, so we'll do the same on cannonlake. BUG=b:71722386 BRANCH=none TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip all the bits. Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/25069/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2187f90..ca2f9a3 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -200,6 +200,9 @@ mainboard_silicon_init_params(params); + /* Unlock upper 8 bytes of RTC RAM */ + params->PchLockDownRtcMemoryLock = 0; + /* SATA */ params->SataEnable = config->SataEnable; params->SataMode = config->SataMode; -- To view, visit https://review.coreboot.org/25069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b Gerrit-Change-Number: 25069 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 08 Mar '18

08 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68400/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22825/ : SUCCESS -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 09 Mar 2018 00:56:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add support for GSPI
by build bot (Jenkins) (Code Review) 08 Mar '18

08 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24906 ) Change subject: soc/intel/apollolake: Add support for GSPI ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68399/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22824/ : SUCCESS -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Mar 2018 00:55:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/glkrvp: Wake eMMC HW early during boot
by Bora Guvendik (Code Review) 08 Mar '18

08 Mar '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/25065 ) Change subject: mb/intel/glkrvp: Wake eMMC HW early during boot ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Iba93e9f9f3d7731883aac3c4f887f72cc7fbcdc6 Gerrit-Change-Number: 25065 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: commonlib/storage: Make pci sdhci code compile in romstage
by Bora Guvendik (Code Review) 08 Mar '18

08 Mar '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/25004 ) Change subject: commonlib/storage: Make pci sdhci code compile in romstage ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ifdc3572e3ef30e3ce1e58e6ec062344305d4e439 Gerrit-Change-Number: 25004 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: commonlib/storage: Make sd_mmc_go_idle an api
by Bora Guvendik (Code Review) 08 Mar '18

08 Mar '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/25003 ) Change subject: commonlib/storage: Make sd_mmc_go_idle an api ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I016e1b596a0c8a9ba72be29948648ae4c0cc7b1f Gerrit-Change-Number: 25003 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/glkrvp: Wake eMMC HW early during boot
by Bora Guvendik (Code Review) 08 Mar '18

08 Mar '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/25005 ) Change subject: mb/intel/glkrvp: Wake eMMC HW early during boot ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I0f5bc1e971e17bd3b048aa39bbe804147f1816a7 Gerrit-Change-Number: 25005 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/glkrvp: Wake eMMC HW early during boot
by Bora Guvendik (Code Review) 08 Mar '18

08 Mar '18

Bora Guvendik has restored this change. ( https://review.coreboot.org/25005 ) Change subject: mb/intel/glkrvp: Wake eMMC HW early during boot ...................................................................... Restored -- To view, visit https://review.coreboot.org/25005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: restore Gerrit-Change-Id: I0f5bc1e971e17bd3b048aa39bbe804147f1816a7 Gerrit-Change-Number: 25005 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit March 2018