coreboot-gerrit March 2018

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Change in coreboot[master]: mb/google/kahlee:Fix IRQ routing
by Richard Spiegel (Code Review) 12 Mar '18

12 Mar '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25107 Change subject: mb/google/kahlee:Fix IRQ routing ...................................................................... mb/google/kahlee:Fix IRQ routing Current IRQ tables (firmware and ACPI) are based in the assumption of a non-existent IOAPIC redirection table, which probably existed when the code was in UEFI environment. Coreboot does not work with redirection table, instead it relies on much simpler virtual wire. Therefor both table have to be fixed to use virtual wire. BUG=b:74104946 TEST=Build and boot kahlee and grunt, verify that neither is broken. Someone else will need to verify if PCIe interrupt are working. Change-Id: Ibb048d3e728dc562cb31b9ddd50bfd8fb032017e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl 2 files changed, 39 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/25107/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e82569e..e1f5915 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -43,16 +43,14 @@ * MP Tables. TODO: Make ACPI use these values too. */ -// TODO: Move these to board variant specific file -#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE) const u8 mainboard_picr_data[] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x18] = 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x30] = 0x05, 0x04, 0x00, 0x00, 0x04, 0x05, 0x00, 0x00, [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -65,15 +63,15 @@ }; const u8 mainboard_intr_data[] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x00] = 0X14, 0x15, 0x16, 0x17, 0x1F, 0x1F, 0x1F, 0x1F, [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x10] = 0x09, 0x1F, 0x1F, 0x12, 0x1F, 0x1F, 0x1F, 0x13, [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x30] = 0x0C, 0x0D, 0x12, 0x11, 0x0C, 0x0D, 0x12, 0x00, [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -82,45 +80,6 @@ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -#else -const u8 mainboard_picr_data[] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, -}; - -const u8 mainboard_intr_data[] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -#endif /* * This table defines the index into the picr/intr_data tables for each diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index c61bc4bb..4bbb0fc 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -50,7 +50,7 @@ Package() { 0x0012FFFF, 0, INTC, 0 }, Package() { 0x0012FFFF, 1, INTB, 0 }, - /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + /* Bus 0, Dev 16 Func 0 - USB: xHCI */ Package() { 0x0010FFFF, 0, INTC, 0 }, Package() { 0x0010FFFF, 1, INTB, 0 }, @@ -65,14 +65,14 @@ /* Bus 0, Dev 0 - F15 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package() { 0x0001FFFF, 0, 0, 43 }, - Package() { 0x0001FFFF, 1, 0, 40 }, + Package() { 0x0001FFFF, 0, 0, 17 }, + Package() { 0x0001FFFF, 1, 0, 18 }, /* Bus 0, Dev 2 - PCIe Bridges */ - Package() { 0x0002FFFF, 0, 0, 44 }, - Package() { 0x0002FFFF, 1, 0, 45 }, - Package() { 0x0002FFFF, 2, 0, 46 }, - Package() { 0x0002FFFF, 3, 0, 47 }, + Package() { 0x0002FFFF, 0, 0, 26 }, + Package() { 0x0002FFFF, 1, 0, 23 }, + Package() { 0x0002FFFF, 2, 0, 24 }, + Package() { 0x0002FFFF, 3, 0, 25 }, /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ @@ -82,15 +82,15 @@ Package() { 0x0014FFFF, 3, 0, 19 }, /* Bus 0, Dev 18 Func 0 - USB: EHCI */ - Package() { 0x0012FFFF, 0, 0, 18 }, - Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 0, 0, 12 }, + Package() { 0x0012FFFF, 1, 0, 13 }, /* Bus 0, Dev 10 Func 0 - USB: xHCI */ - Package() { 0x0010FFFF, 0, 0, 18}, - Package() { 0x0010FFFF, 1, 0, 17}, + Package() { 0x0010FFFF, 0, 0, 12}, + Package() { 0x0010FFFF, 1, 0, 13}, /* Bus 0, Dev 17 - SATA controller */ - Package() { 0x0011FFFF, 0, 0, 19 }, + Package() { 0x0011FFFF, 0, 0, 5 }, }) @@ -105,10 +105,10 @@ Name (APS4, Package() { /* PCIe slot - Hooked to PCIe slot 4 */ - Package() { 0x0000FFFF, 0, 0, 24 }, - Package() { 0x0000FFFF, 1, 0, 25 }, - Package() { 0x0000FFFF, 2, 0, 26 }, - Package() { 0x0000FFFF, 3, 0, 27 }, + Package() { 0x0000FFFF, 0, 0, 0 }, + Package() { 0x0000FFFF, 1, 0, 1 }, + Package() { 0x0000FFFF, 2, 0, 2 }, + Package() { 0x0000FFFF, 3, 0, 3 }, }) /* GPP 1 */ @@ -121,10 +121,10 @@ }) Name (APS5, Package() { - Package() { 0x0000FFFF, 0, 0, 28 }, - Package() { 0x0000FFFF, 1, 0, 29 }, - Package() { 0x0000FFFF, 2, 0, 30 }, - Package() { 0x0000FFFF, 3, 0, 31 }, + Package() { 0x0000FFFF, 0, 0, 8 }, + Package() { 0x0000FFFF, 1, 0, 9 }, + Package() { 0x0000FFFF, 2, 0, 10 }, + Package() { 0x0000FFFF, 3, 0, 11 }, }) /* GPP 2 */ @@ -137,10 +137,10 @@ }) Name (APS6, Package() { - Package() { 0x0000FFFF, 0, 0, 32 }, - Package() { 0x0000FFFF, 1, 0, 33 }, - Package() { 0x0000FFFF, 2, 0, 34 }, - Package() { 0x0000FFFF, 3, 0, 35 }, + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, }) /* GPP 3 */ @@ -153,10 +153,10 @@ }) Name (APS7, Package() { - Package() { 0x0000FFFF, 0, 0, 36 }, - Package() { 0x0000FFFF, 1, 0, 37 }, - Package() { 0x0000FFFF, 2, 0, 38 }, - Package() { 0x0000FFFF, 3, 0, 39 }, + Package() { 0x0000FFFF, 0, 0, 24 }, + Package() { 0x0000FFFF, 1, 0, 25 }, + Package() { 0x0000FFFF, 2, 0, 26 }, + Package() { 0x0000FFFF, 3, 0, 27 }, }) /* GPP 4 */ @@ -168,8 +168,8 @@ }) Name (APS8, Package() { - Package() { 0x0000FFFF, 0, 0, 40 }, - Package() { 0x0000FFFF, 1, 0, 41 }, - Package() { 0x0000FFFF, 2, 0, 42 }, - Package() { 0x0000FFFF, 3, 0, 43 }, + Package() { 0x0000FFFF, 0, 0, 0 }, + Package() { 0x0000FFFF, 1, 0, 1 }, + Package() { 0x0000FFFF, 2, 0, 2 }, + Package() { 0x0000FFFF, 3, 0, 3 }, }) -- To view, visit https://review.coreboot.org/25107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibb048d3e728dc562cb31b9ddd50bfd8fb032017e Gerrit-Change-Number: 25107 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/intel/broadwell: add support for Intel GMA OpRegion
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25094 ) Change subject: soc/intel/broadwell: add support for Intel GMA OpRegion ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22891/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68473/ : SUCCESS -- To view, visit https://review.coreboot.org/25094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I024f4f0784df3cbbb9977692e9ef0ff9c3552725 Gerrit-Change-Number: 25094 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Prabal Saha <coolstarorganization(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Mar 2018 14:44:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]drivers/spi: Add status register lockdown
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25106 ) Change subject: [WIP]drivers/spi: Add status register lockdown ...................................................................... Patch Set 1: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68470/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22890/ : FAILURE -- To view, visit https://review.coreboot.org/25106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If99fc7d61692e3926cd1a92e40c9d64f8fa5463d Gerrit-Change-Number: 25106 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Mar 2018 14:32:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]drivers/spi: Add status register lockdown
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25106 ) Change subject: [WIP]drivers/spi: Add status register lockdown ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22889/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/68470/ : FAILURE -- To view, visit https://review.coreboot.org/25106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If99fc7d61692e3926cd1a92e40c9d64f8fa5463d Gerrit-Change-Number: 25106 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Mar 2018 14:21:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]drivers/spi: Winbond specific writeprotection enable
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: [WIP]drivers/spi: Winbond specific writeprotection enable ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22888/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68472/ : SUCCESS -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Mar 2018 14:17:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]src/drivers/spi: Read Winbond's flash protection bits
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25082 ) Change subject: [WIP]src/drivers/spi: Read Winbond's flash protection bits ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68471/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22887/ : SUCCESS -- To view, visit https://review.coreboot.org/25082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Gerrit-Change-Number: 25082 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 12 Mar 2018 14:11:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]drivers/spi: Add status register lockdown
by Patrick Rudolph (Code Review) 12 Mar '18

12 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25106 Change subject: [WIP]drivers/spi: Add status register lockdown ...................................................................... [WIP]drivers/spi: Add status register lockdown Implement status register lockdown for Winbond devices. Change-Id: If99fc7d61692e3926cd1a92e40c9d64f8fa5463d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/spi_flash.h 3 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/25106/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 769ef48..86a3a9f 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -474,6 +474,21 @@ return flash->ops->set_write_protection(flash, region); } +int spi_flash_lock(const struct spi_flash *flash) +{ + if (!flash) + return -1; + + if (flash->ops->lock_status_register) { + printk(BIOS_WARNING, "SPI: Locking status register is not " + "implemented for this vendor.\n"); + return 0; + } + + return flash->ops->lock_status_register(flash); +} + + static uint32_t volatile_group_count CAR_GLOBAL; int spi_flash_volatile_group_begin(const struct spi_flash *flash) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 2992dc3..bea0c05 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -18,6 +18,7 @@ #define CMD_W25_RDSR 0x05 /* Read Status Register */ #define CMD_W25_WRSR 0x01 /* Write Status Register */ #define CMD_W25_RDSR2 0x35 /* Read Status2 Register */ +#define STS_W25_SRL 0x01 /* Status Register Lock */ #define CMD_W25_WRSR2 0x31 /* Write Status2 Register */ #define CMD_W25_RDSR3 0x15 /* Read Status3 Register */ #define CMD_W25_WRSR3 0x11 /* Write Status3 Register */ @@ -474,6 +475,14 @@ return winbond_set_b_protect_protection(flash, region); } +static int winbond_lock_status_register(const struct spi_flash *flash) +{ + u8 reg = STS_W25_SRL; + + return spi_flash_cmd(&flash->spi, CMD_W25_WRSR2, &reg, + sizeof(reg)); +} + static const struct spi_flash_ops spi_flash_ops = { .write = winbond_write, .erase = spi_flash_cmd_erase, @@ -485,6 +494,7 @@ #endif .get_write_protection = winbond_get_write_protection, .set_write_protection = winbond_set_write_protection, + .lock_status_register = winbond_lock_status_register, }; int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index d1dfa92..ae86c42 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -44,6 +44,7 @@ const struct region *region); int (*set_write_protection)(const struct spi_flash *flash, const struct region *region); + int (*lock_status_register)(const struct spi_flash *flash); }; struct spi_flash { @@ -133,6 +134,19 @@ const struct region *region); /* + * Active software status register lockdown. + * After the execution of this command, the flash regions marked as read-only, + * can't be written to, until the next power cycle. + * + * @param flash : A SPI flash device + * + * Returns: + * -1 on error + * 0 on success + */ +int spi_flash_lock(const struct spi_flash *flash); + +/* * Some SPI controllers require exclusive access to SPI flash when volatile * operations like erase or write are being performed. In such cases, * volatile_group_begin will gain exclusive access to SPI flash if not already -- To view, visit https://review.coreboot.org/25106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If99fc7d61692e3926cd1a92e40c9d64f8fa5463d Gerrit-Change-Number: 25106 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: [WIP]drivers/spi: Winbond specific writeprotection enable
by Patrick Rudolph (Code Review) 12 Mar '18

12 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25105 Change subject: [WIP]drivers/spi: Winbond specific writeprotection enable ...................................................................... [WIP]drivers/spi: Winbond specific writeprotection enable Extend the SPI interface to enable write protection. Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/spi_flash.h 3 files changed, 196 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/25105/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 9bad9f3..769ef48 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -452,6 +452,28 @@ return flash->ops->get_write_protection(flash, region); } +int spi_flash_set_write_protected(const struct spi_flash *flash, + const struct region *region) +{ + struct region flash_region = { 0 }; + + if (!flash) + return -1; + + flash_region.size = flash->size; + + if (!region_is_subregion(&flash_region, region)) + return -1; + + if (flash->ops->set_write_protection) { + printk(BIOS_WARNING, "SPI: Setting write-protection is not " + "implemented for this vendor.\n"); + return 0; + } + + return flash->ops->set_write_protection(flash, region); +} + static uint32_t volatile_group_count CAR_GLOBAL; int spi_flash_volatile_group_begin(const struct spi_flash *flash) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 6c1ce0d..2992dc3 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -31,6 +31,8 @@ #define CMD_W25_DP 0xb9 /* Deep Power-down */ #define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ #define CMD_W25_B_LOCK_STATUS 0x3d /* Read Block/Sector Lock bit */ +#define CMD_W25_B_LOCK_SET 0x36 /* Set Block/Sector Lock bit */ +#define CMD_W25_B_LOCK_CLEAR 0x39 /* Clear Block/Sector Lock bit */ struct winbond_spi_flash_params { uint16_t id; @@ -319,9 +321,157 @@ return ret; } if (reg & STS_W25_WPS) - return winbond_read_b_lock_protection(flash, region); + return winbond_get_b_lock_protection(flash, region); else - return winbond_read_b_protect_protection(flash, region); + return winbond_get_b_protect_protection(flash, region); +} + +/* + * Only available on some devices. + * Set Block Protection Bits of each block. + * + * Returns: + * -1 on error + * 0 on success + */ +static int winbond_set_b_lock_protection(const struct spi_flash *flash, + const struct region *region) +{ + int ret, i; + u8 cmd[5], reg8; + + cmd[4] = 0x00; + + /* Writeable */ + cmd[0] = CMD_W25_B_LOCK_CLEAR; + for (i = 0; i < region->offset; i += flash->sector_size) { + cmd[1] = (i >> 16) & 0xff; + cmd[2] = (i >> 8) & 0xff; + cmd[3] = i & 0xff; + + ret = spi_flash_cmd_ext(&flash->spi, cmd, sizeof(cmd), + &reg8, sizeof(reg8)); + if (ret) + return ret; + } + + /* Readonly */ + cmd[0] = CMD_W25_B_LOCK_SET; + for (i = 0; i < region->size; i += flash->sector_size) { + cmd[1] = ((region->offset + i) >> 16) & 0xff; + cmd[2] = ((region->offset + i) >> 8) & 0xff; + cmd[3] = (region->offset + i) & 0xff; + + ret = spi_flash_cmd_ext(&flash->spi, cmd, sizeof(cmd), + &reg8, sizeof(reg8)); + if (ret) + return ret; + } + + /* Writeable */ + cmd[0] = CMD_W25_B_LOCK_CLEAR; + for (i = region->offset + region->size; i < flash->size; + i += flash->sector_size) { + cmd[1] = (i >> 16) & 0xff; + cmd[2] = (i >> 8) & 0xff; + cmd[3] = i & 0xff; + + ret = spi_flash_cmd_ext(&flash->spi, cmd, sizeof(cmd), + &reg8, sizeof(reg8)); + if (ret) + return ret; + } + return 1; +} + +/* + * Available on all devices. + * Write block protect bits to Status/Status2 Reg. + * + * Returns: + * -1 on error + * 0 on success + */ +static int winbond_set_b_protect_protection(const struct spi_flash *flash, + const struct region *region) +{ + int ret, shift, block; + union { + u8 u; + struct { + u8 busy : 1; + u8 wel : 1; + u8 bp : 3; + u8 tb : 1; + u8 sec : 1; + u8 srp0 : 1; + } s; + } reg1 = {.u = 0}; + union { + u8 u; + struct { + u8 : 6; + u8 cmp : 1; + u8 : 1; + } s; + } reg2 = {.u = 0}; + + /* Need to touch TOP or BOTTOM */ + if (region->offset == 0 || + region->offset + region->size == flash->size) + return -1; + + reg1.s.tb = region->offset == 0; + + reg1.s.sec = region->size < flash->block_size; + + if (reg1.s.sec && (region->size > flash->block_size / 2)) + return -1; + + if (reg1.s.sec) + block = flash->sector_size; + else + block = max(flash->block_size, flash->size / 64); + + if (region->size > 0) { + for (shift = 0; shift <= 0x7; shift++) { + if (region->size == block << shift) + break; + } + if (shift > 0x7) + return -1; + reg1.s.bp = shift; + } else + reg1.s.bp = 0; + + ret = spi_flash_cmd(&flash->spi, CMD_W25_WRSR, &reg1.u, sizeof(reg1.u)); + if (ret) + return ret; + + return spi_flash_cmd(&flash->spi, CMD_W25_WRSR2, &reg2.u, + sizeof(reg2.u)); +} + +static int winbond_set_write_protection(const struct spi_flash *flash, + const struct region *region) +{ + u8 reg = STS_W25_WPS; + + /* Check alignment */ + if (region->offset & (flash->sector_size - 1)) + return -1; + if (region->size & (flash->sector_size - 1)) + return -1; + + if (IS_ENABLED(CONFIG_SPI_FLASH_HAS_BLOCK_LOCK_BITS)) { + int ret = spi_flash_cmd(&flash->spi, CMD_W25_WRSR3, &reg, + sizeof(reg)); + if (ret) + return ret; + return winbond_set_b_lock_protection(flash, region); + } + + return winbond_set_b_protect_protection(flash, region); } static const struct spi_flash_ops spi_flash_ops = { @@ -334,6 +484,7 @@ .read = spi_flash_cmd_read_fast, #endif .get_write_protection = winbond_get_write_protection, + .set_write_protection = winbond_set_write_protection, }; int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 82705d4..d1dfa92 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -42,7 +42,8 @@ int (*status)(const struct spi_flash *flash, u8 *reg); int (*get_write_protection)(const struct spi_flash *flash, const struct region *region); - + int (*set_write_protection)(const struct spi_flash *flash, + const struct region *region); }; struct spi_flash { @@ -113,6 +114,25 @@ int spi_flash_is_write_protected(const struct spi_flash *flash, const struct region *region); /* + * Enable the vendor dependent SPI flash write protection. The region not + * covered by write-protection will be set to write-able state. + * Only a single write-protected region is supported. + * Some flash ICs require the region to be aligned in the block size, sector + * size or page size. + * Some flash ICs require the region to start at TOP or BOTTOM. + * + * @param flash : A SPI flash device + * @param region: A subregion of the device's region + * + * Returns: + * -1 on error + * -1 if the region alignment is bad + * 0 on success + */ +int spi_flash_set_write_protected(const struct spi_flash *flash, + const struct region *region); + +/* * Some SPI controllers require exclusive access to SPI flash when volatile * operations like erase or write are being performed. In such cases, * volatile_group_begin will gain exclusive access to SPI flash if not already -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Enable SAR configs
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25104 ) Change subject: mb/google/poppy/variants/nautilus: Enable SAR configs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22886/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68469/ : SUCCESS -- To view, visit https://review.coreboot.org/25104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11a8fa04a77f688ed288780f2c605b8ac701f5a9 Gerrit-Change-Number: 25104 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Mar 2018 13:42:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Use internal pulldown for MEM_CONFIG_4
by build bot (Jenkins) (Code Review) 12 Mar '18

12 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25103 ) Change subject: mb/google/poppy/variants/nami: Use internal pulldown for MEM_CONFIG_4 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22885/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68468/ : SUCCESS -- To view, visit https://review.coreboot.org/25103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4 Gerrit-Change-Number: 25103 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Mar 2018 13:35:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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