coreboot-gerrit March 2018

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Change in coreboot[master]: util/inteltool: Add some Skylake desktop ids
by build bot (Jenkins) (Code Review) 13 Mar '18

13 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25144 ) Change subject: util/inteltool: Add some Skylake desktop ids ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68518/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22930/ : SUCCESS -- To view, visit https://review.coreboot.org/25144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Gerrit-Change-Number: 25144 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Mar 2018 19:45:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP inteltool: Add dumping of full PCR ports
by build bot (Jenkins) (Code Review) 13 Mar '18

13 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19593 ) Change subject: WIP inteltool: Add dumping of full PCR ports ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22928/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68516/ : SUCCESS -- To view, visit https://review.coreboot.org/19593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Gerrit-Change-Number: 19593 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Mar 2018 19:41:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
by build bot (Jenkins) (Code Review) 13 Mar '18

13 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25142 ) Change subject: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22926/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68514/ : SUCCESS -- To view, visit https://review.coreboot.org/25142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Gerrit-Change-Number: 25142 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Mar 2018 19:37:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP inteltool: Dump GPIO groups in devicetree format
by build bot (Jenkins) (Code Review) 13 Mar '18

13 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19590 ) Change subject: WIP inteltool: Dump GPIO groups in devicetree format ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22927/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68515/ : SUCCESS -- To view, visit https://review.coreboot.org/19590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I159c02dc466d0d2fce8cbd54117cc699c74d1abd Gerrit-Change-Number: 19590 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Mar 2018 19:37:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/inteltool: Add some Skylake desktop ids
by Nico Huber (Code Review) 13 Mar '18

13 Mar '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25144 Change subject: util/inteltool: Add some Skylake desktop ids ...................................................................... util/inteltool: Add some Skylake desktop ids Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c 5 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/25144/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 594959a..e561282 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1005,6 +1005,7 @@ gpio_registers = baytrail_score_ssus_gpio_registers; size = ARRAY_SIZE(baytrail_score_ssus_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: print_gpio_groups(sb, false); return 0; diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index dd66f03..3937507 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -566,6 +566,7 @@ const struct gpio_community *const *communities; switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: community_count = ARRAY_SIZE(sunrise_communities); communities = sunrise_communities; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index c9f961a..6429a7c 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -122,6 +122,8 @@ "6th generation (Skylake-S/H family) Core Processor (Workstation)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D, "6th generation (Skylake-S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, + "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 016199d..736d5f1 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -227,6 +227,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 67a29a7..7f05ebc 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -218,6 +218,7 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: -- To view, visit https://review.coreboot.org/25144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Gerrit-Change-Number: 25144 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: util/inteltool: Report Skylake GPIOs as clumsy coreboot macros
by Nico Huber (Code Review) 13 Mar '18

13 Mar '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25145 Change subject: util/inteltool: Report Skylake GPIOs as clumsy coreboot macros ...................................................................... util/inteltool: Report Skylake GPIOs as clumsy coreboot macros Change-Id: Id8895f5d76ba2984fbda757fc00a42ac0ae852d4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/inteltool/gpio_groups.c 1 file changed, 149 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/25145/1 diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 3937507..6d9cd6d 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -510,6 +510,148 @@ return "RESERVED"; } +static const char *decode_table_gpio_term(const size_t term) +{ + switch (term) { + case 0: return "NONE"; + case 2: return "5K_PD"; + case 4: return "20K_PD"; + case 9: return "1K_PU"; + case 10: return "5K_PU"; + case 11: return "2K_PU"; + case 12: return "20K_PU"; + case 13: return "667_PU"; + case 15: return "NATIVE"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_reset(const size_t reset) +{ + switch (reset) { + case 0: return "DSW_PWROK"; + case 1: return "DEEP"; + case 2: return "PLTRST"; + case 3: return "RSMRST"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_nf(const size_t pad_mode) +{ + switch (pad_mode) { + case 0: return "GPIO"; + case 1: return "NF1"; + case 2: return "NF2"; + case 3: return "NF3"; + default: return "UNSUPPORTED"; + } +} + +static int print_table_gpio(const struct gpio_group *const group, + const size_t pad, + const uint32_t dw0, const uint32_t dw1) +{ + /* 3032 */ + const size_t tx_state = dw0 >> 0 & 1; + const size_t tx_disable = dw0 >> 8 & 1; + const size_t rx_disable = dw0 >> 9 & 1; + const size_t pad_mode = dw0 >> 10 & 7; + const size_t int_route = dw0 >> 17 & 0x0f; + const size_t rx_invert = dw0 >> 23 & 1; + const size_t rx_evcfg = dw0 >> 25 & 3; + const size_t rx_raw1 = dw0 >> 28 & 1; + const size_t rx_padsel = dw0 >> 29 & 1; + const size_t pad_reset = dw0 >> 30 & 3; + const size_t term = dw1 >> 10 & 0x0f; + const size_t pad_tol = dw1 >> 25 & 0x01; + + const char *const pad_name = group->pad_names[pad * group->func_count]; + + if (rx_padsel || rx_raw1) + return -1; + + if (pad_mode) { + printf("PAD_CFG_NF%s(%s, %s, %s, %s),\n", + pad_tol ? "_1V8" : "", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_nf(pad_mode)); + } else if (!tx_disable) { + if (!rx_disable) { + fprintf(stderr, "WARNING: %s has both TX and RX enabled" + ", disabling RX!\n", pad_name); + } + if (term) { + printf("PAD_CFG_TERM_GPO(%s, %zu, %s, %s),\n", + pad_name, tx_state, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPO(%s, %zu, %s),\n", + pad_name, tx_state, + decode_table_gpio_reset(pad_reset)); + } + } else if (!rx_disable && tx_disable) { + switch (int_route) { + case 0x0: + if (rx_invert || rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI%s(%s, %s, %s%s),\n", + rx_evcfg ? "_INT" : "", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + rx_evcfg ? ", EDGE" : ""); + break; + case 0x1: + return -1; + case 0x2: + if (rx_evcfg == 1) { + printf("PAD_CFG_GPI_ACPI_SMI" + "(%s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + rx_invert ? "YES" : "NO"); + } else { + return -1; + } + break; + case 0x4: + if (rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI_ACPI_SCI%s(%s, %s, %s, %s),\n", + rx_evcfg ? "" : "_LEVEL", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + rx_invert ? "YES" : "NO"); + break; + case 0x8: + if (rx_evcfg > 1 || (rx_evcfg == 1 && rx_invert)) + return -1; + printf("PAD_CFG_GPI_APIC%s(%s, %s, %s),\n", + rx_evcfg ? "_EDGE" : rx_invert ? "_INVERT" : "", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + break; + default: + return -1; + } + } else { + if (term) { + printf("_PAD_CFG(%s, %s, %s),\n", pad_name, + decode_table_gpio_term(term), + "_DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, " + "NO, NO, NO, NO, GPIO, YES, YES)"); + } else { + printf("PAD_CFG_NC(%s),\n", pad_name); + } + } + return 0; +} + static void print_gpio_group(const uint8_t pid, size_t pad_cfg, const struct gpio_group *const group) { @@ -521,10 +663,13 @@ const uint32_t dw0 = read_pcr32(pid, pad_cfg); const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4); - printf("0x%04zx: 0x%016"PRIx64" %-8s %-20s\n", pad_cfg, - (uint64_t)dw1 << 32 | dw0, - group->pad_names[p * group->func_count], - decode_pad_mode(group, p, dw0)); + printf("0x%04zx: /* %-8s %-20s 0x%016"PRIx64" */ ", + pad_cfg, group->pad_names[p * group->func_count], + decode_pad_mode(group, p, dw0), + (uint64_t)dw1 << 32 | dw0); + + if (print_table_gpio(group, p, dw0, dw1)) + printf("PAD_CFG_UNSUPPORTED,\n"); } } -- To view, visit https://review.coreboot.org/25145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id8895f5d76ba2984fbda757fc00a42ac0ae852d4 Gerrit-Change-Number: 25145 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: util/inteltool: Add missing #include <string.h>
by Nico Huber (Code Review) 13 Mar '18

13 Mar '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25143 Change subject: util/inteltool: Add missing #include <string.h> ...................................................................... util/inteltool: Add missing #include <string.h> Change-Id: I7bb142d9f936b73e84d301028069d85cc15d596a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/inteltool/inteltool.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/25143/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index a92dbc35..c9f961a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -18,6 +18,7 @@ #include <stdio.h> #include <stdlib.h> +#include <string.h> #include <inttypes.h> #include <getopt.h> #include <fcntl.h> -- To view, visit https://review.coreboot.org/25143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7bb142d9f936b73e84d301028069d85cc15d596a Gerrit-Change-Number: 25143 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: payloads: Add LinuxBoot payload in u-root mode
by Philipp Deppenwiese (Code Review) 13 Mar '18

13 Mar '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/23071 ) Change subject: payloads: Add LinuxBoot payload in u-root mode ...................................................................... Patch Set 21: Evaluate xz --check=crc32 -9 --lzma2=dict=1MiB --stdout /tmp/initramfs.linux_amd64.cpio | dd bs=512 of=/tmp/initramfs.linux_amd64.cpio.xz -- To view, visit https://review.coreboot.org/23071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659 Gerrit-Change-Number: 23071 Gerrit-PatchSet: 21 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chris K <c(a)chrisko.ch> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich Gerrit-CC: Burke Cates <burke.cates(a)gmail.com> Gerrit-Comment-Date: Tue, 13 Mar 2018 18:41:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
by build bot (Jenkins) (Code Review) 13 Mar '18

13 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25142 ) Change subject: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22925/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68513/ : SUCCESS -- To view, visit https://review.coreboot.org/25142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Gerrit-Change-Number: 25142 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Mar 2018 17:55:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
by Richard Spiegel (Code Review) 13 Mar '18

13 Mar '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25142 Change subject: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code ...................................................................... soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code Devices that need to have their AOAC register enabled do have a delay before they become available. Currently each device has their own wait loop. As UART also needs AOAC, it's better to program all AOAC devices before calling any device initialization, then do the UART initialization (without the AOAC initialization, but waiting AOAC completion) and finally do a check/loop for all other AOAC devices. Create a procedure that initializes all AOAC devices in a table, then call this new procedure before the call to initialize the UART. Then change all procedures that initialize some AOAC by moving the devices to the table and removing AOAC initialization code. BUG=b:74416098 TEST=Build and boot kahlee checking that UART is sending debug messages out. Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 29 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25142/1 diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 3eff5eb..f85644c 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -73,6 +73,7 @@ bootblock_soc_init(); /* APs will not return */ bootblock_fch_early_init(); + enable_aoac_devices(); post_code(0x90); if (CONFIG_STONEYRIDGE_UART) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cccdf97..6cc1c79 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -342,6 +342,7 @@ uint8_t control; }; +void enable_aoac_devices(void); void sb_enable_rom(void); void configure_stoneyridge_uart(void); void configure_stoneyridge_i2c(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 367c565..f028d1a 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -32,6 +32,23 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed at configure_stoneyridge_uart(). All other devices need only + * to verify if their AOAC is already enabled, and do a minimal delay + * if needed. + */ +static int aoac_devices[] = { + (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), + FCH_AOAC_D3_CONTROL_AMBA, + FCH_AOAC_D3_CONTROL_I2C0, + FCH_AOAC_D3_CONTROL_I2C1, + FCH_AOAC_D3_CONTROL_I2C2, + FCH_AOAC_D3_CONTROL_I2C3 +}; + static int is_sata_config(void) { return !((CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) @@ -296,15 +313,18 @@ return false; } +void enable_aoac_devices(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devices); i++) + power_on_aoac_device(aoac_devices[i]); +} + void configure_stoneyridge_uart(void) { bool status; - /* Power on the UART and AMBA devices */ - power_on_aoac_device(FCH_AOAC_D3_CONTROL_UART0 - + CONFIG_UART_FOR_CONSOLE * 2); - power_on_aoac_device(FCH_AOAC_D3_CONTROL_AMBA); - /* Set the GPIO mux to UART */ write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); @@ -324,19 +344,14 @@ { bool status; - /* Power on the I2C devices */ - power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0); - power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1); - power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2); - power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3); - /* Wait for the I2C devices to indicate power and clock OK */ do { - udelay(100); status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + if (!status) + udelay(10); } while (!status); } -- To view, visit https://review.coreboot.org/25142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Gerrit-Change-Number: 25142 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit March 2018