coreboot-gerrit March 2018

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Change in coreboot[master]: mb/google/octopus: Configure early GPIOs early
by Justin TerAvest (Code Review) 16 Mar '18

16 Mar '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25250 Change subject: mb/google/octopus: Configure early GPIOs early ...................................................................... mb/google/octopus: Configure early GPIOs early GPIOs for TPM communication (I2C, interrupt) and EEPROM write-protect should be configured early, before romstage. This change configures those pads earlier. These GPIOs match in the existing Octopus schematics. BUG=None TEST=None Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/25250/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index d06de1a..a031dbb 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -82,12 +82,9 @@ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_55, 0, DEEP, NONE, HIZCRx0, ENPU), /* LPSS_I2C2_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C4_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C4_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* UART0-CTS_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */ @@ -237,7 +234,6 @@ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_DATA */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_0 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_190, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_1 */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ @@ -265,6 +261,13 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* I2C TPM */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C4_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C4_SCL */ + + PAD_CFG_GPI_APIC_IOS(GPIO_63, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* TPM PCH_INT_ODL */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_190, 0, DEEP, NONE, TxDRxE, DISPUPD), /* PCH_WP_OD */ + }; const struct pad_config *__attribute__((weak)) -- To view, visit https://review.coreboot.org/25250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214 Gerrit-Change-Number: 25250 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: soc/intel/apollolake: Add PCIe de-emphasis enable configuration.
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25185 ) Change subject: soc/intel/apollolake: Add PCIe de-emphasis enable configuration. ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23099/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68705/ : SUCCESS -- To view, visit https://review.coreboot.org/25185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0 Gerrit-Change-Number: 25185 Gerrit-PatchSet: 7 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 19:05:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Configure PERST_0 pin
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25248 ) Change subject: mb/google/octopus: Configure PERST_0 pin ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23098/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68703/ : SUCCESS -- To view, visit https://review.coreboot.org/25248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Gerrit-Change-Number: 25248 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 18:58:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Add PCIe de-emphasis enable configuration.
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25185 ) Change subject: soc/intel/apollolake: Add PCIe de-emphasis enable configuration. ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68704/ : ABORTED -- To view, visit https://review.coreboot.org/25185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0 Gerrit-Change-Number: 25185 Gerrit-PatchSet: 6 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 18:55:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vendorcode/intel:Update FSP Header files per v2.0.0
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25247 ) Change subject: vendorcode/intel:Update FSP Header files per v2.0.0 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23097/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68702/ : SUCCESS -- To view, visit https://review.coreboot.org/25247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 Gerrit-Change-Number: 25247 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 18:52:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Configure PERST_0 pin
by Justin TerAvest (Code Review) 16 Mar '18

16 Mar '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25248 Change subject: mb/google/octopus: Configure PERST_0 pin ...................................................................... mb/google/octopus: Configure PERST_0 pin According to the schematic, Octopus boards have WLAN_PE_RST connected to GPIO_164. This change configures that properly in devicetree. BUG=None TEST=None Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/25248/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 9d267cf..934699c 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -3,6 +3,9 @@ device lapic 0 on end end + # GPIO for PERST_0 (WLAN_PE_RST) + register "prt0_gpio" = "GPIO_164" + # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-16.33. # [14:8] steps of delay for HS400, each 125ps. -- To view, visit https://review.coreboot.org/25248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Gerrit-Change-Number: 25248 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: vendorcode/intel:Update FSP Header files per v2.0.0
by Srinidhi N Kaushik (Code Review) 16 Mar '18

16 Mar '18

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/25247 Change subject: vendorcode/intel:Update FSP Header files per v2.0.0 ...................................................................... vendorcode/intel:Update FSP Header files per v2.0.0 Update FSP header files to match GLK FSP Reference Code Release v2.0.0 Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 2 files changed, 73 insertions(+), 118 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25247/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h index acbc596..4559e22 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -52,6 +52,9 @@ #define MAX_SPD_SAVE 29 #endif +#define MRC_DDR_TYPE_LPDDR4 6 +#define MRC_DDR_TYPE_DDR4 7 + // // MRC version description. // @@ -805,11 +808,9 @@ **/ UINT32 OemLoadingBase; -/** Offset 0x0120 - OEM File Name to Load - Specify a file name to load from CSE file system after memory is available. Empty - indicates no file needs to be loaded. +/** Offset 0x0120 **/ - UINT8 OemFileName[16]; + UINT8 Reserved[16]; /** Offset 0x0130 **/ @@ -962,37 +963,41 @@ **/ VOID* VariableNvsBufferPtr; -/** Offset 0x0164 +/** Offset 0x0164 - PERST pin for RootPort 0 + Address for PERST pin for Rootport 0. For Intel RVP, address of N_GPIO_105. 0x00C507D0(Default). +**/ + UINT32 RootPort0Perst; + +/** Offset 0x0168 - PERST pin for RootPort 1 + Address for PERST pin for Rootport 1. For Intel RVP, address of A_GPIO_163. 0x00C90670(Default). +**/ + UINT32 RootPort1Perst; + +/** Offset 0x016C - PERST pin for RootPort 2 + Address for PERST pin for Rootport 2. For Intel RVP, address of N_GPIO_137. 0x00C509D0(Default). +**/ + UINT32 RootPort2Perst; + +/** Offset 0x0170 - PERST pin for RootPort 3 + Address for PERST pin for Rootport 3. +**/ + UINT32 RootPort3Perst; + +/** Offset 0x0174 - PERST pin for RootPort 4 + Address for PERST pin for Rootport 4. For Intel RVP, address of SCC_GPIO_210. 0x00C806D0(Default). +**/ + UINT32 RootPort4Perst; + +/** Offset 0x0178 - PERST pin for RootPort 5 + Address for PERST pin for Rootport 5. +**/ + UINT32 RootPort5Perst; + +/** Offset 0x017C **/ UINT8 ReservedFspmUpd[4]; } FSP_M_CONFIG; -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0168 -**/ - UINT32 Signature; - -/** Offset 0x016C -**/ - UINT8 ReservedFspmTestUpd[20]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0180 -**/ - UINT32 Signature; - -/** Offset 0x0184 -**/ - UINT8 ReservedFspmRestrictedUpd[124]; -} FSP_M_RESTRICTED_CONFIG; - /** Fsp M UPD Configuration **/ typedef struct { @@ -1009,17 +1014,9 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0168 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - /** Offset 0x0180 **/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x0200 -**/ - UINT8 UnusedUpdSpace1[6]; + UINT8 UnusedUpdSpace1[134]; /** Offset 0x0206 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index e4839e0..cc50058 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -1672,74 +1672,40 @@ **/ UINT16 HgSubSystemId; -/** Offset 0x0388 +/** Offset 0x0388 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV, + 100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port. **/ - UINT8 ReservedFspsUpd[8]; + UINT8 Usb2AfePetxiset[8]; + +/** Offset 0x0390 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV, + 100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port. +**/ + UINT8 Usb2AfeTxiset[8]; + +/** Offset 0x0398 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2AfePredeemp[8]; + +/** Offset 0x03A0 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2AfePehalfbit[8]; + +/** Offset 0x03A8 - Intel Processor Trace output Scheme method + Intel Processor Trace output Scheme method 0:Single Range Output (Default) 1. ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x03A9 +**/ + UINT8 ReservedFspsUpd[7]; } FSP_S_CONFIG; -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x0390 -**/ - UINT32 Signature; - -/** Offset 0x0394 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S Restricted Configuration -**/ -typedef struct { - -/** Offset 0x03A0 -**/ - UINT32 Signature; - -/** Offset 0x03A4 - Selective enable SGX - Selective enable SGX. 0xFFFF(Default). -**/ - UINT16 SelectiveEnableSgx; - -/** Offset 0x03A6 - SGX debug mode - Select SGX mode. 0:Disable(default), 1:Enable - 0:Disable(default), 1:Enable -**/ - UINT8 SgxDebugMode; - -/** Offset 0x03A7 - SGX Launch Control Policy Mode - Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default) - 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode -**/ - UINT8 SgxLcp; - -/** Offset 0x03A8 - LE KeyHash0 - LE KeyHash0. 0x0(Default). -**/ - UINT64 SgxLePubKeyHash0; - -/** Offset 0x03B0 - LE KeyHash1 - LE KeyHash1. 0x0(Default). -**/ - UINT64 SgxLePubKeyHash1; - -/** Offset 0x03B8 - LE KeyHash2 - LE KeyHash2. 0x0(Default). -**/ - UINT64 SgxLePubKeyHash2; - -/** Offset 0x03C0 - LE KeyHash3 - LE KeyHash3. 0x0(Default). -**/ - UINT64 SgxLePubKeyHash3; - -/** Offset 0x03C8 -**/ - UINT8 ReservedFspsRestrictedUpd[8]; -} FSP_S_RESTRICTED_CONFIG; - /** Fsp S UPD Configuration **/ typedef struct { @@ -1752,19 +1718,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0390 +/** Offset 0x03B0 **/ - FSP_S_TEST_CONFIG FspsTestConfig; + UINT8 UnusedUpdSpace7[78]; -/** Offset 0x03A0 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x03D0 -**/ - UINT8 UnusedUpdSpace7[6]; - -/** Offset 0x03D6 +/** Offset 0x03FE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/25247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 Gerrit-Change-Number: 25247 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Call sb_spibase() early
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25246 ) Change subject: soc/amd/stoneyridge: Call sb_spibase() early ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23096/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68701/ : SUCCESS -- To view, visit https://review.coreboot.org/25246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Gerrit-Change-Number: 25246 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 18:25:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/flash: Add SPI flash protection
by build bot (Jenkins) (Code Review) 16 Mar '18

16 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25196 ) Change subject: security/flash: Add SPI flash protection ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23095/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68700/ : SUCCESS -- To view, visit https://review.coreboot.org/25196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I12656d7c111ed3622fab5578f6e0c462fe5d4796 Gerrit-Change-Number: 25196 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Mar 2018 18:24:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Call sb_spibase() early
by Garrett Kirkendall (Code Review) 16 Mar '18

16 Mar '18

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25246 Change subject: soc/amd/stoneyridge: Call sb_spibase() early ...................................................................... soc/amd/stoneyridge: Call sb_spibase() early Call sb_spibase() early so that it will set up the SPI base address. This is another step to moving AGESA calls out of the bootblock. BUG=b:74427893 BRANCH=master TEST=Build and boot Grunt. Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25246/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b4dcd8f..cf059a4 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -559,6 +559,7 @@ sb_enable_rom(); sb_lpc_port80(); sb_lpc_decode(); + sb_spibase(); sb_acpi_mmio_decode(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/25246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Gerrit-Change-Number: 25246 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com>

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coreboot-gerrit March 2018