coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add VT-d and VMX programming
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25118 ) Change subject: soc/intel/cannonlake: Add VT-d and VMX programming ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68766/ : SUCCESS -- To view, visit https://review.coreboot.org/25118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e Gerrit-Change-Number: 25118 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 22:47:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/kahlee: Update GPIOs based on board ID
by Martin Roth (Code Review) 19 Mar '18

19 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25287 Change subject: mainboard/google/kahlee: Update GPIOs based on board ID ...................................................................... mainboard/google/kahlee: Update GPIOs based on board ID BUG=b:73078053 TEST=build & boot Grunt Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 4 files changed, 75 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25287/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 1eb18f1..a7207b0 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -19,6 +19,7 @@ #include <soc/southbridge.h> #include <variant/ec.h> #include <variant/gpio.h> +#include <boardid.h> void bootblock_mainboard_early_init(void) { @@ -30,6 +31,16 @@ gpios = variant_early_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); + + /* TODO: Remove when no longer needed */ + /* Program additional early GPIOs */ + if (board_id() < 2) { + gpios = variant_early_gpio_table_old(&num_gpios); + sb_program_gpios(gpios, num_gpios); + } else { + gpios = variant_early_gpio_table_new(&num_gpios); + sb_program_gpios(gpios, num_gpios); + } } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e82569e..2a1c3eb 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -30,6 +30,7 @@ #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <boardid.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -168,6 +169,13 @@ gpios = variant_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); + /* TODO: Remove when no longer needed */ + /* Reprogram additional GPIOs */ + if (board_id() < 2) { + gpios = variant_gpio_table_old(&num_gpios); + sb_program_gpios(gpios, num_gpios); + } + gpes = get_gpe_table(&num); gpe_configure_sci(gpes, num); diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index cab7611..2e0a07e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -83,9 +83,6 @@ /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */ - PAD_GPI(GPIO_40, PULL_UP), - /* GPIO_42 - S5_MUX_CTRL */ PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE), @@ -110,9 +107,6 @@ /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), - /* GPIO_93 - EMMC_RST_L */ - PAD_GPO(GPIO_93, HIGH), - /* GPIO_95 - SD_CLK */ /* GPIO_96 - SD_CMD */ /* GPIO_97 - SD_D0 */ @@ -195,6 +189,22 @@ PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_new[] = { + /* GPIO_40 - EMMC_BRIDGE_RST */ + PAD_GPI(GPIO_40, PULL_DOWN), + + /* GPIO_93 - EMMC_RST */ + PAD_GPO(GPIO_93, LOW), +}; + +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = { + /* GPIO_40 - EMMC_BRIDGE_RST_L */ + PAD_GPI(GPIO_40, PULL_UP), + + /* GPIO_93 - EMMC_RST_L */ + PAD_GPO(GPIO_93, HIGH), +}; + const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), @@ -202,8 +212,8 @@ /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), - /* GPIO_12 - Unused (TP126) */ - PAD_GPI(GPIO_12, PULL_UP), + /* GPIO_12 - EN_PP3300_TRACKPAD */ + PAD_GPO(GPIO_12, HIGH), /* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */ PAD_GPI(GPIO_13, PULL_UP), @@ -233,7 +243,7 @@ PAD_GPO(GPIO_90, HIGH), /* GPIO_91 - EN_PP3300_TRACKPAD */ - PAD_GPO(GPIO_91, HIGH), + PAD_GPI(GPIO_91, PULL_UP), /* GPIO_102 - EN_SD_SOCKET_PWR */ PAD_NF(GPIO_102, SD0_PWR_CTRL, PULL_DOWN), @@ -254,6 +264,15 @@ PAD_GPI(GPIO_135, PULL_UP), }; +const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = { + + /* GPIO_12 - Unused (TP126) */ + PAD_GPI(GPIO_12, PULL_UP), + + /* GPIO_91 - EN_PP3300_TRACKPAD */ + PAD_GPO(GPIO_91, HIGH), +}; + const __attribute__((weak)) struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) { @@ -268,6 +287,28 @@ return gpio_set_stage_ram; } +/* TODO: Remove when no longer needed */ +const __attribute__((weak)) +struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_old(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset_old); + return gpio_set_stage_reset_old; +} + +const __attribute__((weak)) +struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_new(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset_new); + return gpio_set_stage_reset_new; +} + +const __attribute__((weak)) +struct soc_amd_stoneyridge_gpio *variant_gpio_table_old(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram_old); + return gpio_set_stage_ram_old; +} + /* * GPE setup table must match ACPI GPE ASL * { gevent, gpe, direction, level } diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index e5a348a..9744113 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -31,5 +31,11 @@ int variant_get_ehci_oc_map(uint16_t *usb_oc_map); const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size); const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size); +/* TODO: Remove when no longer needed */ +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_old( \ + size_t *size); +const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_new( \ + size_t *size); +const struct soc_amd_stoneyridge_gpio *variant_gpio_table_old(size_t *size); #endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/25287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Gerrit-Change-Number: 25287 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mainboard/google/kahlee: Initialize EC earlier in the bootblock
by Martin Roth (Code Review) 19 Mar '18

19 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25286 Change subject: mainboard/google/kahlee: Initialize EC earlier in the bootblock ...................................................................... mainboard/google/kahlee: Initialize EC earlier in the bootblock Set up the EC communication a little earlier so we can read the board ID before programming GPIOS. BUG=b:73078053 TEST=Build & Boot grunt, board_id() now gets ID correctly Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/bootblock/bootblock.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/25286/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index acdffe5..1eb18f1 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -24,15 +24,16 @@ { size_t num_gpios; const struct soc_amd_stoneyridge_gpio *gpios; + + /* Enable the EC as soon as we have visibility */ + mainboard_ec_init(); + gpios = variant_early_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); } void bootblock_mainboard_init(void) { - /* Enable the EC as soon as we have visibility */ - mainboard_ec_init(); - /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); -- To view, visit https://review.coreboot.org/25286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5 Gerrit-Change-Number: 25286 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/google/octopus: Create bip variant
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25285 ) Change subject: mb/google/octopus: Create bip variant ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23151/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68765/ : SUCCESS -- To view, visit https://review.coreboot.org/25285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda Gerrit-Change-Number: 25285 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 22:46:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Create bip variant
by Justin TerAvest (Code Review) 19 Mar '18

19 Mar '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/25285 Change subject: mb/google/octopus: Create bip variant ...................................................................... mb/google/octopus: Create bip variant This creates a bip variant for octopus. Nothing is set in the variant files here-- everything is picked up from baseboard. BUG=b:75976864 TEST=None Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/bip/include/variant/ec.h A src/mainboard/google/octopus/variants/bip/include/variant/gpio.h 5 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/25285/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3321b5c..49d5248 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -36,6 +36,7 @@ config VARIANT_DIR string default "yorp" if BOARD_GOOGLE_YORP + default "bip" if BOARD_GOOGLE_BIP default "octopus" if BOARD_GOOGLE_OCTOPUS config DEVICETREE @@ -45,6 +46,7 @@ config MAINBOARD_PART_NUMBER string default "yorp" if BOARD_GOOGLE_YORP + default "bip" if BOARD_GOOGLE_BIP default "octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY @@ -55,6 +57,7 @@ string depends on CHROMEOS default "YORP TEST 7755" if BOARD_GOOGLE_YORP + default "BIP TEST 5732" if BOARD_GOOGLE_BIP default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS config MAX_CPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index fa72b49..f4bd02c 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -6,3 +6,7 @@ bool "Yorp" select BOARD_GOOGLE_BASEBOARD_OCTOPUS select BASEBOARD_OCTOPUS_LAPTOP +config BOARD_GOOGLE_BIP + bool "Bip" + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select BASEBOARD_OCTOPUS_LAPTOP diff --git a/src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/bip/include/variant/ec.h b/src/mainboard/google/octopus/variants/bip/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/bip/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/bip/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bip/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bip/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/25285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda Gerrit-Change-Number: 25285 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: drivers/intel/wifi: Add Jefferson Peak Device ID
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25146 ) Change subject: drivers/intel/wifi: Add Jefferson Peak Device ID ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23149/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68762/ : SUCCESS -- To view, visit https://review.coreboot.org/25146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48886cea5578a302f6ef033cb35df4a38bd64ea8 Gerrit-Change-Number: 25146 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 22:12:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Re-size flash WP_RO segment
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25253 ) Change subject: mb/google/octopus: Re-size flash WP_RO segment ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68761/ : SUCCESS -- To view, visit https://review.coreboot.org/25253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a0d1d0121b503ff390adf3ce25973d72e59fdeb Gerrit-Change-Number: 25253 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 21:22:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/glkrvp: Re-size flash WP_RO segment
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25255 ) Change subject: mb/intel/glkrvp: Re-size flash WP_RO segment ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68760/ : SUCCESS -- To view, visit https://review.coreboot.org/25255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8b24422e1eef2d0a81006286d4fc58f238fdce11 Gerrit-Change-Number: 25255 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 21:14:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/flash: Refactor flash protection logic
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25283 ) Change subject: security/flash: Refactor flash protection logic ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68759/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23148/ : SUCCESS -- To view, visit https://review.coreboot.org/25283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic0a859e6ce9aba32278f666a38a952ec8b4c1b4d Gerrit-Change-Number: 25283 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 21:08:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/flash: Refactor flash protection logic
by Philipp Deppenwiese (Code Review) 19 Mar '18

19 Mar '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25283 to look at the new patch set (#3). Change subject: security/flash: Refactor flash protection logic ...................................................................... security/flash: Refactor flash protection logic Change-Id: Ic0a859e6ce9aba32278f666a38a952ec8b4c1b4d Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/drivers/mrc_cache/mrc_cache.c M src/drivers/spi/spi_flash.c M src/security/flash/Makefile.inc M src/security/flash/flash.c M src/security/flash/flash.h A src/security/flash/wp.c M src/security/vboot/vboot_handoff.c 7 files changed, 94 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/25283/3 -- To view, visit https://review.coreboot.org/25283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic0a859e6ce9aba32278f666a38a952ec8b4c1b4d Gerrit-Change-Number: 25283 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit March 2018