coreboot-gerrit March 2018

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Change in coreboot[master]: [WIP]soc/intel/cannonlake: Clear EMMC timeout for USB boot
by Bora Guvendik (Code Review) 20 Mar '18

20 Mar '18

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25290 Change subject: [WIP]soc/intel/cannonlake: Clear EMMC timeout for USB boot ...................................................................... [WIP]soc/intel/cannonlake: Clear EMMC timeout for USB boot Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. _PS0 is not called by OS during USB boot but OS still initializes emmc. Add _INI to cover USB boot case. BUG=b.71586766 TEST=Install OS into EMMC Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/acpi/scs.asl 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/25290/1 diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 4062e70..7e9195a 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -31,6 +31,12 @@ PGEN, 1, /* PG_ENABLE */ } + Method(_INI) { + /* Clear register 0x1C20/0x4820 */ + ^^PCRA (PID_EMMC, 0x1C20, 0x0) + ^^PCRA (PID_EMMC, 0x4820, 0x0) + } + Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us @@ -80,6 +86,13 @@ PGEN, 1, /* PG_ENABLE */ } + Method(_INI) + { + /* Clear register 0x1C20/0x4820 */ + ^^PCRA (PID_SDX, 0x1C20, 0x0) + ^^PCRA (PID_SDX, 0x4820, 0x0) + } + Method (_PS0, 0, Serialized) { Store (0, PGEN) /* Disable PG */ -- To view, visit https://review.coreboot.org/25290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11 Gerrit-Change-Number: 25290 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: intel/fsp: Update Cannonlake FSP header
by Lijian Zhao (Code Review) 20 Mar '18

20 Mar '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25289 Change subject: intel/fsp: Update Cannonlake FSP header ...................................................................... intel/fsp: Update Cannonlake FSP header Update Cannonlake FSP header to version 7.x.2A.20, the following changes had been made: 1. Add MemtestonWarmBoot option. 2. Add enable8254clockgatingonS3 option. 3. Default disable Tccoffsetlock BUG=None TEST=None Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 2 files changed, 21 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25289/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index d014f81..74cc672 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -2291,9 +2291,15 @@ **/ UINT8 PegImrRpSelection; -/** Offset 0x0513 +/** Offset 0x0513 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable **/ - UINT8 ReservedFspmUpd[12]; + UINT8 MemTestOnWarmBoot; + +/** Offset 0x0514 +**/ + UINT8 ReservedFspmUpd[11]; } FSP_M_CONFIG; /** Fsp M Test Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 0f3577a..4daf891 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -2154,9 +2154,17 @@ **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x0752 +/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS **/ - UINT8 UnusedUpdSpace25[2]; + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x0753 +**/ + UINT8 UnusedUpdSpace25; /** Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2472,7 +2480,7 @@ /** Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; <b>1: Enabled </b>. + target; <b>0: Disabled</b>; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; @@ -2886,13 +2894,13 @@ /** Offset 0x0870 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 + Range 0 to 1023875 in Step size of 125 **/ UINT32 PowerLimit4; /** Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 + Range 0 to 1023875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -- To view, visit https://review.coreboot.org/25289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01 Gerrit-Change-Number: 25289 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI
by build bot (Jenkins) (Code Review) 20 Mar '18

20 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25288 ) Change subject: mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/23174/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/68789/ : ABORTED -- To view, visit https://review.coreboot.org/25288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Gerrit-Change-Number: 25288 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Mar 2018 00:23:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI
by Shamile Khan (Code Review) 20 Mar '18

20 Mar '18

Shamile Khan has uploaded a new patch set (#2). ( https://review.coreboot.org/25288 ) Change subject: mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI ...................................................................... mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI BUG=b:73292699 BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/25288/2 -- To view, visit https://review.coreboot.org/25288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Gerrit-Change-Number: 25288 Gerrit-PatchSet: 2 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI
by Shamile Khan (Code Review) 20 Mar '18

20 Mar '18

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/25288 Change subject: mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI ...................................................................... mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FI BUG=b:73292699 BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/25288/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 1174d2c..abd0252 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -3,6 +3,24 @@ device lapic 0 on end end + register "pcie_rp_clkreq_pin[0]" = "3" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak) + # as it is required for detection + register "pcie_rp_deemphasis_enable[0]" = "0" + # Set de-emphasis to default (enabled) for remaining ports + register "pcie_rp_deemphasis_enable[1]" = "1" + register "pcie_rp_deemphasis_enable[2]" = "1" + register "pcie_rp_deemphasis_enable[3]" = "1" + register "pcie_rp_deemphasis_enable[4]" = "1" + register "pcie_rp_deemphasis_enable[5]" = "1" + # GPIO for PERST_0 (WLAN_PE_RST) register "prt0_gpio" = "GPIO_164" -- To view, visit https://review.coreboot.org/25288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Gerrit-Change-Number: 25288 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Add support for GSPI
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24906 ) Change subject: soc/intel/apollolake: Add support for GSPI ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23172/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68787/ : SUCCESS -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 23:41:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23173/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68788/ : SUCCESS -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 23:35:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 8: No Builds Executed -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 19 Mar 2018 23:23:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/kahlee: Initialize EC earlier in the bootblock
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25286 ) Change subject: mainboard/google/kahlee: Initialize EC earlier in the bootblock ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23152/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68767/ : SUCCESS -- To view, visit https://review.coreboot.org/25286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5 Gerrit-Change-Number: 25286 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 22:54:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/kahlee: Update GPIOs based on board ID
by build bot (Jenkins) (Code Review) 19 Mar '18

19 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25287 ) Change subject: mainboard/google/kahlee: Update GPIOs based on board ID ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23153/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68768/ : SUCCESS -- To view, visit https://review.coreboot.org/25287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Gerrit-Change-Number: 25287 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 19 Mar 2018 22:54:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018