coreboot-gerrit March 2018

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Change in coreboot[master]: lib: Add blob_provider functionality
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24992 ) Change subject: lib: Add blob_provider functionality ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22683/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68239/ : SUCCESS -- To view, visit https://review.coreboot.org/24992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30abc5be5d47a4c697c0b94babb068b0f0ae4794 Gerrit-Change-Number: 24992 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 10:48:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/vboot: Replace all region device and map functions
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24995 ) Change subject: security/vboot: Replace all region device and map functions ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68238/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22682/ : SUCCESS -- To view, visit https://review.coreboot.org/24995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e288c7a17cc96d7e65f914f7253aaa4b74d04e8 Gerrit-Change-Number: 24995 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 10:45:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: lib/cbfs: Remove cbfs_boot_map_optionrom from cbfs impl
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24994 ) Change subject: lib/cbfs: Remove cbfs_boot_map_optionrom from cbfs impl ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68237/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22681/ : SUCCESS -- To view, visit https://review.coreboot.org/24994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I57a35d3ce95850d22f79a1045a30b7c6b011bb68 Gerrit-Change-Number: 24994 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 10:44:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/vboot: Extend measurements for all execution flows
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24993 ) Change subject: security/vboot: Extend measurements for all execution flows ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68236/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22680/ : SUCCESS -- To view, visit https://review.coreboot.org/24993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3ddfeabd63aefec152a9bc439a415c37b814f94f Gerrit-Change-Number: 24993 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 10:44:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by Philipp Deppenwiese (Code Review) 05 Mar '18

05 Mar '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 11 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/vboot: Replace all region device and map functions
by Philipp Deppenwiese (Code Review) 05 Mar '18

05 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24995 Change subject: security/vboot: Replace all region device and map functions ...................................................................... security/vboot: Replace all region device and map functions * Use blob_provider to read blobs. Change-Id: I1e288c7a17cc96d7e65f914f7253aaa4b74d04e8 Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/cpu/amd/microcode/microcode.c M src/cpu/intel/microcode/microcode.c M src/cpu/via/nano/update_ucode.c M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_1/vbt.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/net/r8168.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/lib/coreboot_table.c M src/lib/nhlt.c M src/lib/spd_bin.c M src/mainboard/amd/serengeti_cheetah/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/chell/spd/spd.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/lars/spd/spd.c M src/mainboard/google/link/romstage.c M src/mainboard/google/poppy/romstage.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/urara/boardid.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/intel/harcuvar/spd/spd.c M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/iwill/dk8_htx/acpi_tables.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/purism/librem_skl/mainboard.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/intel/common/mrc_cache.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/psp/psp.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/common/mma.c M src/soc/intel/common/vbt.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c M src/soc/intel/quark/romstage/romstage.c M src/soc/nvidia/tegra210/mtc.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/vendorcode/siemens/hwilib/hwilib.c M src/vendorcode/siemens/hwilib/hwilib.h 80 files changed, 265 insertions(+), 368 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/24995/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 601b6f0..a766fd4 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -47,6 +47,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> +#include <blob_provider.h> u8 acpi_checksum(u8 *table, u32 length) { @@ -1004,9 +1005,7 @@ if (fw) return fw; - dsdt_file = cbfs_boot_map_with_leak( - CONFIG_CBFS_PREFIX "/dsdt.aml", - CBFS_TYPE_RAW, &dsdt_size); + dsdt_file = blob_read_map(BLOB_DATA_ACPI_DSDT, &dsdt_size); if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current; @@ -1019,8 +1018,7 @@ return current; } - slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic", - CBFS_TYPE_RAW, &slic_size); + slic_file = blob_read_map(BLOB_DATA_ACPI_SLIC, &slic_size); if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index ec7e733..08bab31 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -21,6 +21,7 @@ #include <cbfs.h> #include <arch/io.h> #include <smp/spinlock.h> +#include <blob_provider.h> #define UCODE_DEBUG(fmt, args...) \ do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while (0) @@ -203,9 +204,9 @@ spin_lock(romstage_microcode_cbfs_lock()); #endif #endif - - ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], - CBFS_TYPE_MICROCODE, &ucode_len); + ucode = blob_read_arbitrary_map( + COREBOOT_REGION, microcode_cbfs_file[i], + CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { UCODE_DEBUG("microcode file not found. Skipping updates.\n"); #ifdef __PRE_RAM__ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 59c3b8a..7deac06 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -21,6 +21,7 @@ #if !defined(__ROMCC__) #include <cbfs.h> #include <console/console.h> +#include <blob_provider.h> #else #include <arch/cbfs.h> #endif @@ -131,9 +132,8 @@ ucode_updates = CBFS_SUBHEADER(microcode_file); microcode_len = ntohl(microcode_file->len); #else - ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE, - &microcode_len); + ucode_updates = + blob_read_map(BLOB_DATA_MICROCODE, &microcode_len); if (ucode_updates == NULL) return NULL; #endif diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 9ff66e7..cde6239 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -21,6 +21,7 @@ #include <cpu/cpu.h> #include <arch/cpu.h> #include <cbfs.h> +#include <blob_provider.h> static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) { @@ -107,8 +108,7 @@ u32 *ucode_data; size_t ucode_len; - ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &ucode_len); + ucode_data = blob_read_map(BLOB_DATA_MICROCODE, &ucode_len); /* Oops, did you forget to include the microcode ? */ if (ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index d9fac36..80e9fe0 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -30,6 +30,7 @@ #include <pc80/i8254.h> #include <string.h> #include <vbe.h> +#include <blob_provider.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> @@ -270,9 +271,8 @@ vbe_set_mode(&mode_info); #if IS_ENABLED(CONFIG_BOOTSPLASH) struct jpeg_decdata *decdata; - unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); + unsigned char *jpeg = + blob_read_map(BLOB_DATA_BOOTSPLASH, NULL); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 876df23..f51b903 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -58,6 +58,7 @@ #include "../../src/lib/jpeg.h" #include <vbe.h> +#include <blob_provider.h> // pointer to VBEInfoBuffer, set by vbe_prepare u8 *vbe_info_buffer = 0; @@ -745,9 +746,8 @@ * cares. */ // int imagesize = 1024*768*2; - unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); + unsigned char *jpeg = + blob_read_map(BLOB_DATA_BOOTSPLASH, NULL); if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 21530a1..2cc0828 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -24,6 +24,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/dimmSpd.h> +#include <blob_provider.h> #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI) #if IS_ENABLED(CONFIG_ARCH_ROMSTAGE_X86_64) || \ @@ -149,9 +150,9 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = blob_read_arbitrary_map( + COREBOOT_REGION, "pci" CONFIG_VGA_BIOS_ID ".rom", + CBFS_TYPE_OPTIONROM, NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index fdd2e6e..8332374 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,6 +27,8 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include <blob_provider.h> + #include "AMD.h" #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) @@ -45,8 +47,7 @@ const void *agesa, *image; size_t file_size; - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); + agesa = blob_read_map(BLOB_CODE_AMD_AGESA, &file_size); if (agesa == NULL) return; diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 906b356..928bbdd 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -27,6 +27,7 @@ #include <spi_flash.h> #include <lib.h> // hexdump #include "fsp_util.h" +#include <blob_provider.h> /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(void *p) { @@ -58,18 +59,12 @@ size_t region_size; if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) { - struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - *mrc_region_ptr = rdev_mmap_full(&rdev); - return region_device_sz(&rdev); - } - *mrc_region_ptr = NULL; - return 0; + *mrc_region_ptr = blob_read_map( + BLOB_DATA_MRC_CACHE_RW_REGION, &region_size); + return region_size; } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - + *mrc_region_ptr = + blob_read_map(BLOB_DATA_MRC_CACHE, &region_size); return region_size; } } diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 92a4c91..57f4191 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -20,6 +20,7 @@ #include <fsp/gop.h> #include <fsp/ramstage.h> #include <fsp/util.h> +#include <blob_provider.h> /* Reading VBT table from flash */ const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) @@ -31,7 +32,7 @@ } vbt; /* Locate the vbt file in cbfs */ - vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, &vbt_size); + vbt.data = blob_read_map(BLOB_DATA_VGA_VBT, &vbt_size); if (!vbt.data) { printk(BIOS_INFO, "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 3dafa00..3b71156 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,6 +34,7 @@ #include <security/vboot/vboot_common.h> #include <vb2_api.h> #include <fsp/memory_init.h> +#include <blob_provider.h> __attribute__((weak)) void mrc_cache_update_hash(const uint8_t *data, size_t size) @@ -359,21 +360,15 @@ { struct fsp_header hdr; enum cb_err status; - struct cbfsf file_desc; - struct region_device file_data; - const char *name = CONFIG_FSP_M_CBFS; + struct region_device fspm; struct memranges memmap; struct range_entry freeranges[2]; if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); - if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + if (blob_read_region_device(BLOB_CODE_INTEL_FSP_M, &fspm)) die("FSPM not available!\n"); - } - - cbfs_file_data(&file_data, &file_desc); /* Build up memory map of romstage address space including CAR. */ memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); @@ -382,9 +377,9 @@ memranges_insert(&memmap, (uintptr_t)_program, _program_size, 0); if (!IS_ENABLED(CONFIG_FSP_M_XIP)) - status = load_fspm_mem(&hdr, &file_data, &memmap); + status = load_fspm_mem(&hdr, &fspm, &memmap); else - status = load_fspm_xip(&hdr, &file_data); + status = load_fspm_xip(&hdr, &fspm); if (status != CB_SUCCESS) die("Loading FSPM failed!\n"); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index bda88d1..2ab037e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -21,6 +21,7 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> +#include <blob_provider.h> struct fsp_header fsps_hdr; @@ -64,7 +65,6 @@ void fsps_load(bool s3wake) { struct fsp_header *hdr = &fsps_hdr; - struct cbfsf file_desc; struct region_device rdev; const char *name = CONFIG_FSP_S_CBFS; void *dest; @@ -84,13 +84,11 @@ return; } - if (cbfs_boot_locate(&file_desc, name, NULL)) { + if (blob_read_region_device(BLOB_CODE_INTEL_FSP_S, &rdev) < 0) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); die("FSPS not available!\n"); } - cbfs_file_data(&rdev, &file_desc); - /* Load and relocate into CBMEM. */ size = region_device_sz(&rdev); dest = cbmem_add(CBMEM_ID_REFCODE, size); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 6b3a999..9773aff 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -18,24 +18,19 @@ #include <string.h> #include <timestamp.h> #include <cbfs.h> +#include <blob_provider.h> void fsp_temp_ram_exit(void) { struct fsp_header hdr; uint32_t status; temp_ram_exit_fn temp_ram_exit; - struct cbfsf file_desc; - struct region_device file_data; - const char *name = CONFIG_FSP_M_CBFS; + struct region_device fsps; - if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); - die("FSPM not available for CAR Exit!\n"); - } + if (blob_read_region_device(BLOB_CODE_INTEL_FSP_S, &fsps)) + die("FSPS not available!\n"); - cbfs_file_data(&file_data, &file_desc); - - if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + if (fsp_validate_component(&hdr, &fsps) != CB_SUCCESS) die("Invalid FSPM header!\n"); temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 4c17017..b9f2e70 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -33,6 +33,7 @@ #include <device/pci_def.h> #include <delay.h> #include <fmap.h> +#include <blob_provider.h> #include "chip.h" #define NIC_TIMEOUT 1000 @@ -93,23 +94,18 @@ static enum cb_err fetch_mac_string_vpd(u8 *macstrbuf) { - struct region_device rdev; void *search_address; size_t search_length; size_t offset; char key[] = "ethernet_mac"; - if (fmap_locate_area_as_rdev("RO_VPD", &rdev)) { + search_address = + blob_read_map(BLOB_DATA_NVRAM_VPD_RO_REGION, &search_length); + if (search_address == NULL) { printk(BIOS_ERR, "Error: Couldn't find RO_VPD region."); return CB_ERR; } - search_address = rdev_mmap_full(&rdev); - if (search_address == NULL) { - printk(BIOS_ERR, "LAN: VPD not found.\n"); - return CB_ERR; - } - search_length = region_device_sz(&rdev); offset = search(key, search_address, strlen(key), search_length); if (offset == search_length) { @@ -132,17 +128,19 @@ static enum cb_err fetch_mac_string_cbfs(u8 *macstrbuf) { - struct cbfsf fh; - uint32_t matchraw = CBFS_TYPE_RAW; + struct region_device rdev; - if (!cbfs_boot_locate(&fh, "rt8168-macaddress", &matchraw)) { - /* check the cbfs for the mac address */ - if (rdev_readat(&fh.data, macstrbuf, 0, MACLEN) != MACLEN) { - printk(BIOS_ERR, "r8168: Error reading MAC from CBFS\n"); + if (blob_read_arbitrary_region_device(COREBOOT_REGION, + "rt8168-macaddress", + CBFS_TYPE_RAW, &rdev) == 0) { + if (rdev_readat(&rdev, macstrbuf, 0, MACLEN) != MACLEN) { + printk(BIOS_ERR, + "r8168: Error reading MAC from CBFS\n"); return CB_ERR; } return CB_SUCCESS; } + return CB_ERR; } diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 928b403..e9eb957 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -28,6 +28,7 @@ #include <cbfs.h> #include <security/vboot/vbnv.h> #include <security/vboot/vbnv_layout.h> +#include <blob_provider.h> /* There's no way around this include guard. option_table.h is autogenerated */ #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) @@ -256,8 +257,7 @@ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct = cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + ct = blob_read_map(BLOB_DATA_NVRAM_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); @@ -359,8 +359,7 @@ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct = cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + ct = blob_read_map(BLOB_DATA_NVRAM_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "cmos_layout.bin could not be found. " "Options are disabled\n"); diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index c5cd86c..03494d9 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -16,6 +16,7 @@ #include <arch/cbfs.h> #else #include <cbfs.h> +#include <blob_provider.h> #endif #include <pc80/mc146818rtc.h> #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) @@ -63,8 +64,8 @@ #ifdef __ROMCC__ walkcbfs("cmos.default"); #else - cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); + blob_read_map(BLOB_DATA_NVRAM_CMOS_DEFAULT, + &length); #endif if (cmos_default) { int i; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 41b79a6..7f20a7f 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -118,7 +118,7 @@ set the FW_DONE bit before jumping to payload. */ nc_fpga_bar0 = bar0_ptr; /* Open hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return; /* Set up FAN controller and temperature monitor according to */ /* capability bits. */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index aeaff28..124ecc2 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -47,6 +47,7 @@ #include <cpu/x86/mtrr.h> #endif #include <commonlib/helpers.h> +#include <blob_provider.h> static struct lb_header *lb_table_init(unsigned long addr) { @@ -507,8 +508,7 @@ #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) { struct cmos_option_table *option_table = - cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + blob_read_map(BLOB_DATA_NVRAM_CMOS_LAYOUT, NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index da94415..1595620 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -20,6 +20,7 @@ #include <nhlt.h> #include <stdlib.h> #include <string.h> +#include <blob_provider.h> #define NHLT_RID 1 #define NHLT_SSID 1 @@ -161,9 +162,8 @@ for (i = 0; i < num_formats; i++) { struct nhlt_format *fmt; - struct cbfsf file; - struct region_device settings; void *settings_data; + size_t settings_data_size; const struct nhlt_format_config *cfg = &formats[i]; fmt = nhlt_add_format(endp, cfg->num_channels, @@ -178,24 +178,17 @@ if (cfg->settings_file == NULL) continue; - /* Find the settings file in CBFS and place it in format. */ - if (cbfs_boot_locate(&file, cfg->settings_file, NULL)) - return -1; - - cbfs_file_data(&settings, &file); - - settings_data = rdev_mmap_full(&settings); + settings_data = + blob_read_arbitrary_map(COREBOOT_REGION, cfg->settings_file, + 0, &settings_data_size); if (settings_data == NULL) return -1; if (nhlt_format_append_config(fmt, settings_data, - region_device_sz(&settings))) { - rdev_munmap(&settings, settings_data); + settings_data_size)) { return -1; } - - rdev_munmap(&settings, settings_data); } return 0; diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 79bda1e..994058a 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -20,6 +20,7 @@ #include <string.h> #include <device/early_smbus.h> #include <device/dram/ddr3.h> +#include <blob_provider.h> static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; @@ -114,13 +115,11 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) { - struct cbfsf fh; - - uint32_t cbfs_type = CBFS_TYPE_SPD; - - if (cbfs_boot_locate(&fh, "spd.bin", &cbfs_type) < 0) + if (blob_read_arbitrary_region_device(COREBOOT_REGION, "spd.bin", + CBFS_TYPE_SPD, spd_rdev) < 0) { + printk(BIOS_ERR, "Can't locate spd.bin.\n"); return -1; - cbfs_file_data(spd_rdev, &fh); + } return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE, CONFIG_DIMM_SPD_SIZE); } @@ -188,8 +187,7 @@ size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); if (spd_file_len < min_len) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 41e12eb..c17774f 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -32,6 +32,7 @@ #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" #include "mainboard.h" +#include <blob_provider.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -173,9 +174,8 @@ default: continue; } - p = cbfs_boot_map_with_leak( - file_name, - CBFS_TYPE_RAW, &p_size); + p = blob_read_arbitrary_map(COREBOOT_REGION, file_name, + CBFS_TYPE_RAW, &p_size); if (!p || p_size < sizeof(acpi_header_t)) continue; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 6911c36..f391f07 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -21,6 +21,7 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> #include <cbfs.h> +#include <blob_provider.h> #include "mb_sysconf.h" #include "mainboard.h" @@ -162,9 +163,8 @@ /* HTX no io apic */ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } - p = cbfs_boot_map_with_leak( - file_name, - CBFS_TYPE_RAW, &p_size); + p = blob_read_arbitrary_map(COREBOOT_REGION, file_name, + CBFS_TYPE_RAW, &p_size); if (!p || p_size < sizeof(acpi_header_t)) continue; memcpy(ssdtx, p, sizeof(acpi_header_t)); diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index 3388322..9be0f4e 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -29,6 +29,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> +#include <blob_provider.h> void pch_enable_lpc(void) { @@ -76,8 +77,7 @@ { void *spd_file; size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (spd_file && spd_file_len >= 1024) { int i; for (i = 0; i < 4; i++) diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 12c876e..1424b49 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 12c876e..1424b49 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 12c876e..1424b49 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index ac99f5c..ca1fd53 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -25,6 +25,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -107,7 +108,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index dd632f3..f4f9574 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 140c814..4dbac68 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -23,6 +23,7 @@ #include <fmap.h> #include <southbridge/intel/bd82x6x/pch.h> #include "onboard.h" +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -115,18 +116,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_read_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_read_map(BLOB_DATA_NVRAM_VPD, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index a100981..2cf05b7 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -35,6 +35,7 @@ #include <device/pci.h> #include <ec/quanta/ene_kb3940q/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <blob_provider.h> static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -187,28 +188,13 @@ size_t search_length = -1; u16 io_base = 0; struct device *ethernet_dev = NULL; - void *vpd_file; if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - vpd_file = rdev_mmap_full(&rdev); - - if (vpd_file != NULL) { - search_length = region_device_sz(&rdev); - search_address = (uintptr_t)vpd_file; - } - } + search_address = (uintptr_t)blob_read_map( + BLOB_DATA_NVRAM_VPD_RO_REGION, &search_length); } else { - vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, - &search_length); - if (vpd_file) { - search_address = (unsigned long)vpd_file; - } else { - search_length = -1; - search_address = 0; - } + search_address = (uintptr_t)blob_read_map( + BLOB_DATA_NVRAM_VPD, &search_length); } /* Initialize the Embedded Controller */ diff --git a/src/mainboard/google/chell/spd/spd.c b/src/mainboard/google/chell/spd/spd.c index 251b6de..e10f753 100644 --- a/src/mainboard/google/chell/spd/spd.c +++ b/src/mainboard/google/chell/spd/spd.c @@ -22,6 +22,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "../gpio.h" #include "spd.h" @@ -95,8 +96,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index a3db2ed..b61e92c 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -27,6 +27,7 @@ #include <string.h> #include <spd_bin.h> #include "spd_util.h" +#include <blob_provider.h> __attribute__ ((weak)) uint8_t get_ramid(void) { @@ -66,8 +67,7 @@ int dual_channel = 0; /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index 2f365a7..5dd52b8 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -22,6 +22,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "../gpio.h" #include "spd.h" @@ -98,8 +99,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 251b6de..e10f753 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -22,6 +22,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "../gpio.h" #include "spd.h" @@ -95,8 +96,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 59ed111..b3ed9d6 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <soc/pch.h> #include "onboard.h" +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -115,18 +116,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_read_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_read_map(BLOB_DATA_NVRAM_VPD, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c index 106eb83..8f1837d 100644 --- a/src/mainboard/google/lars/spd/spd.c +++ b/src/mainboard/google/lars/spd/spd.c @@ -20,6 +20,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "spd.h" @@ -86,8 +87,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index bf05be9..6a91dd7 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -36,6 +36,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> +#include <blob_provider.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -122,8 +123,7 @@ int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 6bb4076..cf954b5 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include <fsp/soc_binding.h> @@ -122,8 +123,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 25fe859..bea433c 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -21,6 +21,7 @@ #include <soc/mrc_wrapper.h> #include <soc/romstage.h> #include <variant/variant.h> +#include <blob_provider.h> static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { @@ -61,7 +62,7 @@ void *spd_content; int dual_channel = 0; void *spd_file; - size_t spd_fsize; + size_t spd_file_len; struct mrc_params mp = { .mainboard = { @@ -71,12 +72,11 @@ }, }; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); - spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, + spd_content = get_spd_pointer(spd_file, spd_file_len / SPD_SIZE, &dual_channel); mp.mainboard.dram_data[0] = spd_content; if (dual_channel) diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 3d08ad7..2bdf693 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <fmap.h> #include <variant/onboard.h> +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -114,18 +115,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_read_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_read_map(BLOB_DATA_NVRAM_VPD, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 07fe3d9..f30ca4a 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <fmap.h> #include <variant/onboard.h> +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -114,18 +115,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_read_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_read_map(BLOB_DATA_NVRAM_VPD, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 81174db..72c6ee8 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -26,6 +26,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <variant/gpio.h> #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -77,8 +78,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 132f586..2b57b33 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -26,6 +26,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <variant/gpio.h> #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -77,8 +78,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index bf21cbc..607a5be 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -29,6 +29,7 @@ #include <variant/gpio.h> #include "../../onboard.h" #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -80,8 +81,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 5b6b254..c5f79c1 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -28,6 +28,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <variant/gpio.h> #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -79,8 +80,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 9a6b64e..afba754 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -20,6 +20,7 @@ #include <boardid.h> #include <cbfs.h> #include <console/console.h> +#include <blob_provider.h> #include "mainboard/google/urara/urara_boardid.h" @@ -48,8 +49,8 @@ int i; size_t length; - file_contents = cbfs_boot_map_with_leak(board_id_file_name, - CBFS_TYPE_RAW, &length); + file_contents = blob_read_arbitrary_map( + COREBOOT_REGION, board_id_file_name, CBFS_TYPE_RAW, &length); if (!file_contents) { printk(BIOS_WARNING, diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index dbf786e..689ad06 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -23,6 +23,7 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> +#include <blob_provider.h> void pch_enable_lpc(void) { @@ -79,8 +80,7 @@ { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index 37f4424..987f694 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -19,6 +19,7 @@ #include <cbfs.h> #include <console/console.h> #include <string.h> +#include <blob_provider.h> #include "spd.h" @@ -32,8 +33,7 @@ spd_index = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index a17b519..856ac3e 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -21,6 +21,7 @@ #include <soc/pei_wrapper.h> #include "boardid.h" #include "spd.h" +#include <blob_provider.h> void mainboard_fill_dq_map_data(void *dq_map_ptr) { @@ -83,8 +84,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e9818b3..e48cbdd 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -19,6 +19,7 @@ #include "mb_sysconf.h" #include "mainboard.h" #include <cbfs.h> +#include <blob_provider.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -170,9 +171,8 @@ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; } - p = cbfs_boot_map_with_leak( - file_name, - CBFS_TYPE_RAW, &p_size); + p = blob_read_arbitrary_map(COREBOOT_REGION, file_name, + CBFS_TYPE_RAW, &p_size); if (!p || p_size < sizeof(acpi_header_t)) continue; diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 43a3d52..b26d1ca 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -32,6 +32,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "ec.h" +#include <blob_provider.h> #define SPD_LEN 256 @@ -115,8 +116,7 @@ spd_index, mainboard_spd_names[spd_index]); /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) die("SPD data not found."); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 5f7b82e..4ea739a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -36,6 +36,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> +#include <blob_provider.h> void pch_enable_lpc(void) { @@ -75,8 +76,7 @@ size_t spd_file_len; printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/purism/librem_skl/mainboard.c b/src/mainboard/purism/librem_skl/mainboard.c index 462b995..82cecba 100644 --- a/src/mainboard/purism/librem_skl/mainboard.c +++ b/src/mainboard/purism/librem_skl/mainboard.c @@ -16,24 +16,21 @@ #include <smbios.h> #include <string.h> #include <cbfs.h> +#include <blob_provider.h> #define MAX_SERIAL_LENGTH 0x100 const char *smbios_mainboard_serial_number(void) { static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; - struct cbfsf file; + struct region_device cbfs_region; if (serial_number[0] != 0) return serial_number; - if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { - struct region_device cbfs_region; - size_t serial_len; - - cbfs_file_data(&cbfs_region, &file); - - serial_len = region_device_sz(&cbfs_region); + if (blob_read_arbitrary_region_device(COREBOOT_REGION, "serial_number", + 0, &cbfs_region) == 0) { + size_t serial_len = region_device_sz(&cbfs_region); if (serial_len <= MAX_SERIAL_LENGTH) { if (rdev_readat(&cbfs_region, serial_number, 0, serial_len) == serial_len) { diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index d2231aa..1093b21 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -37,6 +37,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" +#include <blob_provider.h> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif @@ -157,8 +158,7 @@ break; } - spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_data = blob_read_map(BLOB_DATA_SPD, &spd_file_len); if (!spd_data) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index fd19cd1..0866c96 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -90,7 +90,7 @@ mapping[i + 4] = buf[chain_len - i - 1]; /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return CB_ERR; /* Now try to find a valid MAC address in hwinfo for this mapping.*/ for (i = 0; i < MAX_NUM_MAPPINGS; i++) { @@ -159,7 +159,7 @@ struct stopwatch sw; /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return; /* Get legacy delay parameter from hwinfo. */ diff --git a/src/mainboard/siemens/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/ptn3460.c index 1877e8b..fb0c95a 100644 --- a/src/mainboard/siemens/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/ptn3460.c @@ -34,7 +34,7 @@ uint8_t edid_data[PTN_EDID_LEN]; int i; - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + if (!hwi_block || hwilib_find_blocks() != CB_SUCCESS) { printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); return 1; diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index ea525d4..37ec517 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -197,7 +197,7 @@ mapping[i + 4] = buf[chain_len - i - 1]; /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return CB_ERR; /* Now try to find a valid MAC address in hwinfo for this mapping.*/ for (i = 0; i < MAX_NUM_MAPPINGS; i++) { @@ -223,7 +223,7 @@ struct stopwatch sw; /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return; /* Get legacy delay parameter from hwinfo. */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index df08471..14d9778 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -46,7 +46,7 @@ uint32_t i; /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return CB_ERR; /* Get first MAC address from hwinfo. */ if (hwilib_get_field(Mac1, mac_adr, sizeof(mac_adr)) != sizeof(mac_adr)) diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 347bc9c..c2f3f9f 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -32,7 +32,7 @@ uint8_t edid_data[0x80]; uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0}; - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + if (!hwi_block || hwilib_find_blocks() != CB_SUCCESS) { printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); return 1; diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 15d949e..f466207 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -174,7 +174,7 @@ /* Get SPD data from hwinfo block and set up memory down */ /* parameters for FSP accordingly. */ - if (hwilib_find_blocks("hwinfo.hex")) { + if (hwilib_find_blocks()) { printk(BIOS_ERR, "HWInfo not found, use default timings for DDR3.\n"); return; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4100b26..5132023 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -31,6 +31,7 @@ #include <string.h> #include "mct_d.h" #include "mct_d_gcc.h" +#include <blob_provider.h> #include "s3utils.h" @@ -56,12 +57,12 @@ ssize_t get_s3nv_file_offset(void) { struct region_device s3nv_region; - struct cbfsf s3nv_cbfs_file; - if (cbfs_boot_locate(&s3nv_cbfs_file, S3NV_FILE_NAME, NULL)) { - printk(BIOS_DEBUG, "S3 state file not found in CBFS: %s\n", S3NV_FILE_NAME); + + if (blob_read_region_device(BLOB_DATA_AMD_S3NV, &s3nv_region)) { + printk(BIOS_DEBUG, "S3 state file not found in CBFS: %s\n", + S3NV_FILE_NAME); return -1; } - cbfs_file_data(&s3nv_region, &s3nv_cbfs_file); return s3nv_region.region.offset; } @@ -213,7 +214,7 @@ s3nv_file_offset = s3nv_offset - s3nv_file_offset; /* Map data structure in CBFS and restore settings */ - s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); + s3nv_cbfs_file_ptr = blob_read_map(BLOB_DATA_AMD_S3NV, NULL); if (!s3nv_cbfs_file_ptr) { printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); return NULL; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index d912317..fe4d7d9 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -24,6 +24,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> +#include <blob_provider.h> void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -293,14 +294,7 @@ const AMD_MODULE_HEADER* module; size_t file_size; - if (IS_ENABLED(CONFIG_VBOOT)) { - /* Use phys. location in flash and prevent vboot from searching cbmem */ - agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; - file_size = 0x100000; - } else { - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); - } + agesa = blob_read_map(BLOB_CODE_AMD_AGESA, &file_size); if (!agesa) return NULL; diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index f692282..7a0b77d 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -26,6 +26,7 @@ #include <spi-generic.h> #include <spi_flash.h> #include "mrc_cache.h" +#include <blob_provider.h> /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { @@ -64,16 +65,11 @@ *mrc_region_ptr = NULL; if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } + *mrc_region_ptr = blob_read_map( + BLOB_DATA_MRC_CACHE_RW_REGION, &region_size); } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); + *mrc_region_ptr = + blob_read_map(BLOB_DATA_MRC_CACHE, &region_size); } return region_size; } diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index f17a374..dbc9a64 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -32,6 +32,7 @@ #include "raminit.h" #include "pei_data.h" #include "haswell.h" +#include <blob_provider.h> void save_mrc_data(struct pei_data *pei_data) { @@ -141,8 +142,7 @@ pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = (unsigned long)cbfs_boot_map_with_leak("mrc.bin", - CBFS_TYPE_MRC, NULL); + entry = (unsigned long)blob_read_map(BLOB_CODE_INTEL_MRC, NULL); if (entry) { int rv; asm volatile ( diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 901a083..730f8a4 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -32,6 +32,7 @@ #include "pei_data.h" #include "sandybridge.h" #include <security/vboot/vboot_common.h> +#include <blob_provider.h> /* Management Engine is in the southbridge */ #include "southbridge/intel/bd82x6x/me.h" @@ -216,7 +217,7 @@ pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + entry = blob_read_map(BLOB_CODE_INTEL_MRC, NULL); if (entry) { int rv; rv = entry (pei_data); diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 5c25d64..23505aa 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -24,6 +24,7 @@ #include <rmodule.h> #include <string.h> #include <timestamp.h> +#include <blob_provider.h> void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {} void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -396,34 +397,24 @@ return Status; } -static int agesa_locate_file(const char *name, struct region_device *rdev, - uint32_t type) -{ - struct cbfsf fh; - - if (cbfs_boot_locate(&fh, name, &type)) - return -1; - - cbfs_file_data(rdev, &fh); - return 0; -} - static int agesa_locate_raw_file(const char *name, struct region_device *rdev) { - return agesa_locate_file(name, rdev, CBFS_TYPE_RAW); + return blob_read_arbitrary_region_device(COREBOOT_REGION, name, + CBFS_TYPE_RAW, rdev); } static int agesa_locate_stage_file_early(const char *name, - struct region_device *rdev) + struct region_device *rdev) { const size_t metadata_sz = sizeof(struct cbfs_stage); - if (agesa_locate_file(name, rdev, CBFS_TYPE_STAGE)) + if (blob_read_arbitrary_region_device(COREBOOT_REGION, name, + CBFS_TYPE_STAGE, rdev)) return -1; /* Peel off the cbfs stage metadata. */ return rdev_chain(rdev, rdev, metadata_sz, - region_device_sz(rdev) - metadata_sz); + region_device_sz(rdev) - metadata_sz); } static int agesa_locate_stage_file_ramstage(const char *name, diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index c05d4de..2304060 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -24,6 +24,7 @@ #include <amdblocks/agesawrapper_call.h> #include <reset.h> #include <soc/southbridge.h> +#include <blob_provider.h> #if ENV_BOOTBLOCK const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -143,9 +144,9 @@ GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo; pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = blob_read_arbitrary_map( + COREBOOT_REGION, "pci" CONFIG_VGA_BIOS_ID ".rom", + CBFS_TYPE_OPTIONROM, NULL); printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", pVbiosImageInfo->ImagePtr); return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING; diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index a1a0e5b..ed7f913 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -21,6 +21,7 @@ #include <bootstate.h> #include <console/console.h> #include <amdblocks/psp.h> +#include <blob_provider.h> static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; static const char *psp_status_halted = "error: PSP in halted state"; @@ -247,16 +248,14 @@ int psp_load_named_blob(int type, const char *name) { void *blob; - struct cbfsf cbfs_file; struct region_device rdev; int r; - if (cbfs_boot_locate(&cbfs_file, name, NULL)) { + if (blob_read_region_device(BLOB_CODE_AMD_PSP, &rdev)) { printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); return PSPSTS_INVALID_NAME; } - cbfs_file_data(&rdev, &cbfs_file); blob = rdev_mmap_full(&rdev); if (blob) { r = psp_load_blob(type, blob); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 45bc75b..e7ee0fe 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -31,6 +31,7 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h> +#include <blob_provider.h> static void reset_system(void) { @@ -140,7 +141,7 @@ } /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { + if (blob_read_map(BLOB_CODE_INTEL_MRC, NULL) == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 665dad2..b9601b9 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -36,6 +36,7 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/systemagent.h> +#include <blob_provider.h> /* * Find PEI executable in coreboot filesystem and execute it. @@ -78,7 +79,7 @@ } /* Determine if mrc.bin is in the cbfs. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + entry = blob_read_map(BLOB_CODE_INTEL_MRC, NULL); if (entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 541a7b4..32de5d2 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/console.h> #include <soc/intel/common/mma.h> +#include <blob_provider.h> #define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" #define MMA_TEST_NAME_TAG "MMA_TEST_NAME" @@ -118,22 +119,15 @@ size_t mma_test_metadata_file_len; char test_filename[TEST_NAME_MAX_SIZE], test_param_filename[TEST_PARAM_MAX_SIZE]; - struct cbfsf metadata_fh, test_content_fh, test_param_fh; + struct cbfsf test_content_fh, test_param_fh; uint32_t mma_type = CBFS_TYPE_MMA; uint32_t efi_type = CBFS_TYPE_EFI; bool metadata_parse_flag = true; printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__); - if (cbfs_locate_file_in_region(&metadata_fh, MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, &mma_type)) { - printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", - MMA_TEST_METADATA_FILENAME); - return -1; - } - - mma_test_metadata = rdev_mmap_full(&metadata_fh.data); - mma_test_metadata_file_len = region_device_sz(&metadata_fh.data); + mma_test_metadata = blob_read_map(BLOB_CODE_INTEL_MMA, + &mma_test_metadata_file_len); if (!mma_test_metadata || !mma_test_metadata_file_len) { printk(BIOS_DEBUG, "MMA: Failed to read %s\n", diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index eba7d40..0087c2e 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <bootmode.h> #include <bootstate.h> +#include <blob_provider.h> #include "vbt.h" @@ -35,19 +36,17 @@ void *locate_vbt(void) { uint32_t vbtsig = 0; - struct cbfsf file_desc; if (vbt_data != NULL) return vbt_data; const char *filename = mainboard_vbt_filename(); - - if (cbfs_boot_locate(&file_desc, filename, NULL) < 0) { + if (blob_read_arbitrary_region_device(COREBOOT_REGION, filename, + CBFS_TYPE_RAW, &vbt_rdev) < 0) { printk(BIOS_ERR, "Could not locate a VBT file in in CBFS\n"); return NULL; } - cbfs_file_data(&vbt_rdev, &file_desc); rdev_readat(&vbt_rdev, &vbtsig, 0, sizeof(uint32_t)); if (vbtsig != VBT_SIGNATURE) { diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index a43504c..efc91ce 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -32,6 +32,7 @@ #include <soc/ramstage.h> #include <soc/fiamux.h> #include <spi-generic.h> +#include <blob_provider.h> static void pci_domain_set_resources(device_t dev) { @@ -104,8 +105,8 @@ const struct microcode *microcode_file; size_t microcode_len; - microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &microcode_len); + microcode_file = + blob_read_map(BLOB_DATA_MICROCODE, &microcode_len); if ((microcode_file != NULL) && (microcode_len != 0)) { /* Update CPU Microcode patch base address/size */ diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 7a9e8f5..cfbd63e 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -28,6 +28,7 @@ #include <soc/romstage.h> #include <chip.h> #include <fsp.h> +#include <blob_provider.h> /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) @@ -61,17 +62,25 @@ UpdData->MemDownEnable = 1; if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) - UpdData->MemDownCh0Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); + UpdData->MemDownCh0Dimm0SpdPtr = + (UINT32)blob_read_arbitrary_map( + COREBOOT_REGION, "spd_ch0_dimm0.bin", + CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) - UpdData->MemDownCh0Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); + UpdData->MemDownCh0Dimm1SpdPtr = + (UINT32)blob_read_arbitrary_map( + COREBOOT_REGION, "spd_ch0_dimm1.bin", + CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) - UpdData->MemDownCh1Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); + UpdData->MemDownCh1Dimm0SpdPtr = + (UINT32)blob_read_arbitrary_map( + COREBOOT_REGION, "spd_ch1_dimm0.bin", + CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) - UpdData->MemDownCh1Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); + UpdData->MemDownCh1Dimm1SpdPtr = + (UINT32)blob_read_arbitrary_map( + COREBOOT_REGION, "spd_ch1_dimm1.bin", + CBFS_TYPE_SPD, NULL); } else { UpdData->MemDownEnable = 0; } diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c5f59c6..b5b8a33 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -23,6 +23,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> +#include <blob_provider.h> static const struct reg_script clear_smi_and_wake_events_script[] = { /* Clear any SMI or wake events */ @@ -65,29 +66,5 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; - size_t fsize; - void *rmu_data; - uint32_t type; - - /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) - return NULL; - - /* Get the file size */ - fsize = region_device_sz(&fh.data); - if (rmu_file_len != NULL) - *rmu_file_len = fsize; - - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); - return rmu_data; + return blob_read_map(BLOB_DATA_MICROCODE_RMU, rmu_file_len); } diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index f71e5e8..29318d0 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <soc/mtc.h> #include <string.h> +#include <blob_provider.h> static size_t mtc_table_size; @@ -28,26 +29,23 @@ int tegra210_run_mtc(void) { ssize_t nread; - struct region_device fh; - struct cbfsf mtc_file; + struct region_device mtc_file; void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS; void *dvfs_table; size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc; - if (cbfs_boot_locate(&mtc_file, "tegra_mtc.bin", NULL)) { + if (blob_read_region_device(BLOB_CODE_NVIDIA_MTC, &mtc_file)) { printk(BIOS_ERR, "MTC file not found: tegra_mtc.bin\n"); return -1; } - cbfs_file_data(&fh, &mtc_file); - /* Read MTC file into predefined region. */ - nread = rdev_readat(&fh, mtc, 0, region_device_sz(&fh)); + nread = rdev_readat(&mtc_file, mtc, 0, region_device_sz(&mtc_file)); - if (nread != region_device_sz(&fh)) { + if (nread != region_device_sz(&mtc_file)) { printk(BIOS_ERR, "MTC bytes read (%zu) != file length(%zu)!\n", - nread, region_device_sz(&fh)); + nread, region_device_sz(&mtc_file)); return -1; } diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 77c0289..75cc044 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -25,6 +25,7 @@ #include <soc/iomap.h> #include <soc/soc_services.h> +#include <blob_provider.h> #include "mbn_header.h" @@ -33,14 +34,13 @@ uint8_t *cdt_ptr; /* pointer to CDT */ }; -static void *load_ipq_blob(const char *file_name) +static void *load_ipq_blob(struct blob_locator identifier) { struct mbn_header *blob_mbn; void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = blob_read_map(identifier, &blob_size); if (!blob_mbn) return NULL; @@ -91,8 +91,8 @@ sbl_rw_ret_info_t (*(*ddr_init_function)(struct cdt_info *cdt_header)); - cdt = load_ipq_blob(CONFIG_CDT_MBN); - ddr_init_function = load_ipq_blob(CONFIG_DDR_MBN); + cdt = load_ipq_blob(BLOB_CODE_QUALCOMM_CDT); + ddr_init_function = load_ipq_blob(BLOB_CODE_QUALCOMM_DDR); if (!cdt || !ddr_init_function) { printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n", @@ -126,7 +126,7 @@ #else /* __PRE_RAM__ */ void start_tzbsp(void) { - void *tzbsp = load_ipq_blob(CONFIG_TZ_MBN); + void *tzbsp = load_ipq_blob(BLOB_CODE_QUALCOMM_TZ); if (!tzbsp) die("could not find or map TZBSP\n"); diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 5b19fc1..9a1e1ab 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -23,17 +23,17 @@ #include <soc/iomap.h> #include <soc/soc_services.h> +#include <blob_provider.h> #include "mbn_header.h" -static void *load_ipq_blob(const char *file_name) +static void *load_ipq_blob(struct blob_locator identifier) { struct mbn_header *blob_mbn; void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = blob_read_map(identifier, &blob_size); if (!blob_mbn) return NULL; @@ -67,8 +67,8 @@ void *cdt; int (*ddr_init_function)(void *cdt_header); - cdt = load_ipq_blob("cdt.mbn"); - ddr_init_function = load_ipq_blob("ddr.mbn"); + cdt = load_ipq_blob(BLOB_CODE_QUALCOMM_CDT); + ddr_init_function = load_ipq_blob(BLOB_CODE_QUALCOMM_DDR); if (!cdt || !ddr_init_function) { printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n", @@ -93,7 +93,7 @@ void start_tzbsp(void) { - void *tzbsp = load_ipq_blob("tz.mbn"); + void *tzbsp = load_ipq_blob(BLOB_CODE_QUALCOMM_TZ); if (!tzbsp) die("could not find or map TZBSP\n"); @@ -118,7 +118,7 @@ return; } - load_addr = (u32) load_ipq_blob("rpm.mbn"); + load_addr = (u32) load_ipq_blob(BLOB_CODE_QUALCOMM_RPM); if (!load_addr) die("could not find or map RPM code\n"); diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index f15937b..87cc26d 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -19,7 +19,7 @@ #include <arch/io.h> #include <arch/early_variables.h> #include "hwilib.h" - +#include <blob_provider.h> #define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd @@ -460,10 +460,9 @@ } /** \brief This function finds all available block types in a given cbfs file. - * @param *hwi_filename Name of the cbfs-file to use. * @return CB_SUCCESS when no error, otherwise error code */ -enum cb_err hwilib_find_blocks (const char *hwi_filename) +enum cb_err hwilib_find_blocks (void) { uint8_t *ptr = NULL, *base = NULL; uint32_t next_offset = 1; @@ -471,13 +470,9 @@ uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); size_t filesize = 0; - /* Check for a valid parameter */ - if (!hwi_filename) - return CB_ERR_ARG; - ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, &filesize); + ptr = blob_read_map(BLOB_DATA_SIEMENS_HWLIB, &filesize); if (!ptr) { - printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", - hwi_filename); + printk(BIOS_ERR,"HWILIB: Missing file HWLIB in cbfs.\n"); return CB_ERR; } /* Ensure the block has the right magic */ diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index 6850f07..41510fa 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -131,7 +131,7 @@ /* Use this function to find all supported blocks in cbfs. It must be called * once with a valid cbfs file name before hwilib_get_field() can be used. */ -enum cb_err hwilib_find_blocks (const char *hwi_filename); +enum cb_err hwilib_find_blocks (void); /* Use this function to get fields out of supported info blocks * This function returns the number of copied bytes or 0 on error. -- To view, visit https://review.coreboot.org/24995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1e288c7a17cc96d7e65f914f7253aaa4b74d04e8 Gerrit-Change-Number: 24995 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: lib/cbfs: Remove cbfs_boot_map_optionrom from cbfs impl
by Philipp Deppenwiese (Code Review) 05 Mar '18

05 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24994 Change subject: lib/cbfs: Remove cbfs_boot_map_optionrom from cbfs impl ...................................................................... lib/cbfs: Remove cbfs_boot_map_optionrom from cbfs impl * Move cbfs_boot_map_optionrom to device/pci_rom.c Change-Id: I57a35d3ce95850d22f79a1045a30b7c6b011bb68 Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/device/pci_rom.c M src/include/cbfs.h M src/lib/cbfs.c 3 files changed, 25 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/24994/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index a411f06..e2a62cb 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -24,11 +24,35 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> -#include <cbfs.h> +#include <blob_provider.h> /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } +static inline int tohex4(unsigned int c) +{ + return (c <= 9) ? (c + '0') : (c - 10 + 'a'); +} + +static void tohex16(unsigned int val, char *dest) +{ + dest[0] = tohex4(val >> 12); + dest[1] = tohex4((val >> 8) & 0xf); + dest[2] = tohex4((val >> 4) & 0xf); + dest[3] = tohex4(val & 0xf); +} + +static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) +{ + char name[17] = "pciXXXX,XXXX.rom"; + + tohex16(vendor, name + 3); + tohex16(device, name + 8); + + return blob_read_arbitrary_map(COREBOOT_REGION, name, + CBFS_TYPE_OPTIONROM, NULL); +} + struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header; diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 1dac504..0dcd0cd 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -23,8 +23,6 @@ * Perform CBFS operations on the boot device. * ***********************************************/ -/* Return mapping of option ROM found in boot device. NULL on error. */ -void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); /* Load stage by name into memory. Returns entry address on success. NULL on * failure. */ void *cbfs_boot_load_stage_by_name(const char *name); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 596abc5..709a9ee 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -141,29 +141,6 @@ } } -static inline int tohex4(unsigned int c) -{ - return (c <= 9) ? (c + '0') : (c - 10 + 'a'); -} - -static void tohex16(unsigned int val, char *dest) -{ - dest[0] = tohex4(val>>12); - dest[1] = tohex4((val>>8) & 0xf); - dest[2] = tohex4((val>>4) & 0xf); - dest[3] = tohex4(val & 0xf); -} - -void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) -{ - char name[17] = "pciXXXX,XXXX.rom"; - - tohex16(vendor, name+3); - tohex16(device, name+8); - - return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); -} - void *cbfs_boot_load_stage_by_name(const char *name) { struct cbfsf fh; -- To view, visit https://review.coreboot.org/24994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I57a35d3ce95850d22f79a1045a30b7c6b011bb68 Gerrit-Change-Number: 24994 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: security/vboot: Extend measurements for all execution flows
by Philipp Deppenwiese (Code Review) 05 Mar '18

05 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24993 Change subject: security/vboot: Extend measurements for all execution flows ...................................................................... security/vboot: Extend measurements for all execution flows * Implement blob_hook_region_device for blob measurements. * Move PCR defines for measured boot into secdata_measurements.c Change-Id: I3ddfeabd63aefec152a9bc439a415c37b814f94f Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/security/tpm/tspi.h M src/security/vboot/secdata_measurements.c 2 files changed, 81 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/24993/1 diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 775311e..bf2b7ae 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -21,34 +21,6 @@ #define TPM_PCR_MAX_LENGTH 64 -// PCR Registers used by coreboot -#define TPM_BOOTBLOCK_PCR 0 -#define TPM_STAGE_VERSTAGE_PCR 0 -#define TPM_STAGE_ROMSTAGE_PCR 1 -#define TPM_STAGE_POSTCAR_PCR 2 -#define TPM_STAGE_RAMSTAGE_PCR 2 -#define TPM_PAYLOAD_PCR 3 -#define TPM_FW_MAIN 1 - -// Vendor / Platform specific -#define TPM_INTEL_FSP_PCR 1 -#define TPM_INTEL_FSPM_PCR 1 -#define TPM_INTEL_FSPS_PCR 1 -#define TPM_INTEL_NHLT_PCR 1 -#define TPM_ARM_BL31_PCR 2 -#define TPM_ARM_BL32_PCR 2 -#define TPM_VGA_OPTION_ROM_PCR 2 -#define TPM_SPD_DATA_PCR 1 -#define TPM_AMD_PSP_PCR 1 -#define TPM_AMD_AGESA_PCR 1 -#define TPM_NVIDIA_MTC_PCR 1 -#define TPM_VBT_PCR 2 -#define TPM_MICROCODE_PCR 1 - -// special -#define TPM_UNKNOWN_PCR 4 - - /** * TPM measurement with acpi log functionality based on binary data. */ diff --git a/src/security/vboot/secdata_measurements.c b/src/security/vboot/secdata_measurements.c index 9111ffa..14b5c27 100644 --- a/src/security/vboot/secdata_measurements.c +++ b/src/security/vboot/secdata_measurements.c @@ -14,11 +14,30 @@ */ #include "antirollback.h" +#include <blob_provider.h> #include <cbfs.h> -#include <fmap.h> #include <console/console.h> +#include <fmap.h> #include <security/tpm/tspi.h> +// CRTM +#define TPM_BOOTBLOCK_PCR 0 +#define TPM_STAGE_VERSTAGE_PCR 0 +#define TPM_STAGE_ROMSTAGE_PCR 0 + +// Soc Init +#define TPM_STAGE_POSTCAR_PCR 1 +#define TPM_STAGE_RAMSTAGE_PCR 1 +#define TPM_INTEL_FSP_PCR 1 + +// Payload +#define TPM_PAYLOAD_PCR 3 +#define TPM_ARM_BL31_PCR 3 +#define TPM_ARM_BL32_PCR 3 + +// Unknown +#define TPM_UNKNOWN_PCR 4 + uint32_t vboot_measure_crtm(void) { struct prog bootblock = PROG_INIT(PROG_BOOTBLOCK, "bootblock"); @@ -29,19 +48,17 @@ /* measure bootblock from RO */ struct cbfsf bootblock_data; - if (!cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL)) { + if (cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL) == + 0) { cbfs_file_data(prog_rdev(&bootblock), &bootblock_data); if (tpm_measure_region(TPM_BOOTBLOCK_PCR, prog_rdev(&bootblock), "bootblock")) { return VB2_ERROR_UNKNOWN; } - - printk(BIOS_INFO, "VBOOT: Couldn't measure %s into CRTM!", - "bootblock"); } else { struct region_device fmap; - if (!fmap_locate_area_as_rdev("BOOTBLOCK", &fmap)) { + if (fmap_locate_area_as_rdev("BOOTBLOCK", &fmap) == 0) { if (tpm_measure_region(TPM_BOOTBLOCK_PCR, &fmap, "bootblock")) { return VB2_ERROR_UNKNOWN; @@ -56,8 +73,8 @@ if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { struct cbfsf romstage_data; /* measure verstage from RO */ - if (!cbfs_boot_locate(&romstage_data, prog_name(&romstage), - NULL)) { + if (cbfs_boot_locate(&romstage_data, prog_name(&romstage), + NULL) == 0) { cbfs_file_data(prog_rdev(&romstage), &romstage_data); if (tpm_measure_region(TPM_STAGE_ROMSTAGE_PCR, @@ -76,8 +93,8 @@ if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { struct cbfsf verstage_data; /* measure verstage from RO */ - if (!cbfs_boot_locate(&verstage_data, prog_name(&verstage), - NULL)) { + if (cbfs_boot_locate(&verstage_data, prog_name(&verstage), + NULL) == 0) { cbfs_file_data(prog_rdev(&verstage), &verstage_data); if (tpm_measure_region(TPM_STAGE_VERSTAGE_PCR, @@ -146,3 +163,57 @@ break; } } + +int blob_hook_region_device(const struct blob_locator locator, + const struct region_device *data) +{ + int pcr_index = TPM_UNKNOWN_PCR; + + switch (locator.id) { + case ID_DATA_BOOTSPLASH: + case ID_DATA_ACPI_SLIC: + case ID_DATA_ACPI_DSDT: + case ID_DATA_ACPI_SSDT: + pcr_index = 2; + break; + case ID_DATA_MICROCODE: + case ID_DATA_MICROCODE_RMU: + case ID_DATA_MRC_CACHE: + case ID_DATA_MRC_CACHE_RW_REGION: + pcr_index = 1; + break; + case ID_DATA_VGA_VBT: + case ID_DATA_NVRAM_CMOS_LAYOUT: + case ID_DATA_NVRAM_CMOS_DEFAULT: + case ID_DATA_NVRAM_VPD: + case ID_DATA_SIEMENS_HWLIB: + case ID_DATA_SPD: + case ID_DATA_MAC: + case ID_DATA_AMD_S3NV: + case ID_DATA_NVRAM_VPD_RO_REGION: + pcr_index = 2; + break; + case ID_CODE_AMD_AGESA: + case ID_CODE_AMD_AGESA_PRE_MEM: + case ID_CODE_AMD_AGESA_POST_MEM: + case ID_CODE_AMD_PSP: + case ID_CODE_INTEL_MRC: + case ID_CODE_INTEL_FSP_S: + case ID_CODE_INTEL_FSP_M: + case ID_CODE_INTEL_MMA: + case ID_CODE_NVIDIA_MTC: + case ID_CODE_QUALCOMM_CDT: + case ID_CODE_QUALCOMM_DDR: + case ID_CODE_QUALCOMM_TZ: + case ID_CODE_QUALCOMM_RPM: + pcr_index = 1; + break; + } + + if (tpm_measure_region(pcr_index, data, locator.cbfs_name) != + TPM_SUCCESS) { + return -1; + } + + return 0; +} -- To view, visit https://review.coreboot.org/24993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3ddfeabd63aefec152a9bc439a415c37b814f94f Gerrit-Change-Number: 24993 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: mb/scaleway/tagada: populate smbios information
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23843 ) Change subject: mb/scaleway/tagada: populate smbios information ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22678/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68233/ : SUCCESS -- To view, visit https://review.coreboot.org/23843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053 Gerrit-Change-Number: 23843 Gerrit-PatchSet: 6 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 10:18:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/denverton_ns: Update UART legacy mode to keep FSP traces
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23623 ) Change subject: soc/intel/denverton_ns: Update UART legacy mode to keep FSP traces ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22679/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68235/ : SUCCESS -- To view, visit https://review.coreboot.org/23623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538 Gerrit-Change-Number: 23623 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: FEI WANG <wangfei.jimei(a)gmail.com> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 05 Mar 2018 10:14:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018