coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

1 participants
1399 discussions

Change in coreboot[master]: google/cyan: fix ACPI interrupt triggering for audio codecs
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24989 ) Change subject: google/cyan: fix ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68266/ : SUCCESS -- To view, visit https://review.coreboot.org/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 16:14:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/intel/braswell: fix PCI resource PMAX/PLEN values
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24985 ) Change subject: soc/intel/braswell: fix PCI resource PMAX/PLEN values ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68267/ : SUCCESS -- To view, visit https://review.coreboot.org/24985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83 Gerrit-Change-Number: 24985 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 16:13:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/soc/amd/stoneyridge: cleanup southbridge.c
by Garrett Kirkendall (Code Review) 05 Mar '18

05 Mar '18

Garrett Kirkendall has removed Marc Jones from this change. ( https://review.coreboot.org/24998 ) Change subject: src/soc/amd/stoneyridge: cleanup southbridge.c ...................................................................... Removed reviewer Marc Jones. -- To view, visit https://review.coreboot.org/24998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Gerrit-Change-Number: 24998 Gerrit-PatchSet: 2 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src/soc/amd/stoneyridge: cleanup southbridge.c
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24998 ) Change subject: src/soc/amd/stoneyridge: cleanup southbridge.c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22709/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68265/ : SUCCESS -- To view, visit https://review.coreboot.org/24998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Gerrit-Change-Number: 24998 Gerrit-PatchSet: 2 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 15:41:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src/soc/amd/stoneyridge: cleanup southbridge.c
by Garrett Kirkendall (Code Review) 05 Mar '18

05 Mar '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24998 to look at the new patch set (#2). Change subject: src/soc/amd/stoneyridge: cleanup southbridge.c ...................................................................... src/soc/amd/stoneyridge: cleanup southbridge.c Limit dependency on vendorcode header files and add appropriate definitions to southbridge.h. Add code to enable decode of FCH ACPI MMIO regions. Factor out to functions, device power-on code for AMBA and UART. Add FCH I2C device power-on code. Add code for FCH to decode TPM memory and IO regions. BUG=b:69220826 b:65442212 BRANCH=master TEST=Build and boot Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Signed-off-by: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 182 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/24998/2 -- To view, visit https://review.coreboot.org/24998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Gerrit-Change-Number: 24998 Gerrit-PatchSet: 2 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/amd/stoneyridge: Create a HALT_THIS_AP callout
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24999 ) Change subject: soc/amd/stoneyridge: Create a HALT_THIS_AP callout ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22708/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68264/ : SUCCESS -- To view, visit https://review.coreboot.org/24999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Gerrit-Change-Number: 24999 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 15:16:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/amd/stoneyridge: Create a HALT_THIS_AP callout
by Richard Spiegel (Code Review) 05 Mar '18

05 Mar '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/24999 Change subject: soc/amd/stoneyridge: Create a HALT_THIS_AP callout ...................................................................... soc/amd/stoneyridge: Create a HALT_THIS_AP callout It was required for all cores use the same CAR teardown function (exit_car.S and gcccar.inc). AGESA has already been modified to do the AP to do the call out. Create assembly code to call chipset_teardown_car and then enter an endless loop with halt instruction. Then create the call out that will call this new assembly code. BUG=b:70338633 TEST=Created a debug version of AGESA that would print the returned status of HALT_THIS_AP. Build code without the fix, see the return. Build code with the fix, see that there's no return. Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/cpu/Makefile.inc A src/soc/amd/common/block/cpu/car/ap_exit_car.S M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h A src/soc/amd/common/block/include/amdblocks/car.h M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/vendorcode/amd/pi/00670F00/AGESA.h 7 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/24999/1 diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index ecc9afbc..fed208a 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1,3 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/ap_exit_car.S +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S + postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S + romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S diff --git a/src/soc/amd/common/block/cpu/car/ap_exit_car.S b/src/soc/amd/common/block/cpu/car/ap_exit_car.S new file mode 100644 index 0000000..82d3413 --- /dev/null +++ b/src/soc/amd/common/block/cpu/car/ap_exit_car.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +.code32 + +#include <cpu/x86/cr.h> + +.globl ap_teardown_car +ap_teardown_car: + pop %edi /* return address */ + pop %esi /* flags */ + + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car + + /* + * Check flags requirements (0 = FALSE, 1 = TRUE) : + * bit 0 = ExecWbinvd + * bit 1 = CacheEn + */ + + test %esi, 1 + jz 1f + wbinvd +1: + test %esi, 2 + jz 2f + /* Enable cache */ + mov %cr0, %eax + and $(~(CR0_CD | CR0_NW)), %eax + mov %eax, %cr0 +2: + cli + hlt + jmp 2b diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index e061c63..34131cf 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -57,6 +57,7 @@ AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr); AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr); +AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr); void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset); void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env); diff --git a/src/soc/amd/common/block/include/amdblocks/car.h b/src/soc/amd/common/block/include/amdblocks/car.h new file mode 100644 index 0000000..60e7c6e --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/car.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_CAR_H__ +#define __AMD_CAR_H__ + +void ap_teardown_car(uint32_t flags); + +#endif /* __AMD_CAR_H__ */ diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index c05d4de..31992e1 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -29,6 +29,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = { { AGESA_DO_RESET, agesa_Reset }, { AGESA_FCH_OEM_CALLOUT, agesa_fch_initreset }, + { AGESA_HALT_THIS_AP, agesa_HaltThisAp }, { AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl } }; #else diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 4ddcedc..f30ed3c 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -26,6 +26,7 @@ #include <amdlib.h> #include <amdblocks/dimm_spd.h> #include "chip.h" +#include <amdblocks/car.h> void __attribute__((weak)) platform_FchParams_reset( FCH_RESET_DATA_BLOCK *FchParams_reset) {} @@ -139,6 +140,24 @@ return AGESA_SUCCESS; } +AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; + uint32_t flags = 0; + + if (info->PrimaryCore == TRUE) + return AGESA_UNSUPPORTED; /* force normal path */ + if (info->ExecWbinvd == TRUE) + flags |= 1; + if (info->CacheEn == TRUE) + flags |= 2; + + ap_teardown_car(flags); /* does not return */ + + /* Should never reach here */ + return AGESA_UNSUPPORTED; +} + /* Allow mainboards to fill the SPD buffer */ __attribute__((weak)) int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h index 17f6986..dc248dd 100644 --- a/src/vendorcode/amd/pi/00670F00/AGESA.h +++ b/src/vendorcode/amd/pi/00670F00/AGESA.h @@ -67,6 +67,7 @@ #define AGESA_RUNFUNC_ON_ALL_APS 0x00028106ul #define AGESA_IDLE_AN_AP 0x00028107ul #define AGESA_WAIT_FOR_ALL_APS 0x00028108ul +#define AGESA_HALT_THIS_AP 0x00028109ul // AGESA ADVANCED CALLOUTS, Memory #define AGESA_READ_SPD 0x00028140ul @@ -2514,6 +2515,14 @@ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference } AGESA_READ_SPD_PARAMS; +/// Parameters structure for the interface call-out AGESA_HALT_THIS_AP +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; + IN BOOLEAN ExecWbinvd; + IN BOOLEAN PrimaryCore; + IN BOOLEAN CacheEn; +} AGESA_HALT_THIS_AP_PARAMS; + /// VoltageType values typedef enum { VTYPE_CPU_VREF, ///< Cpu side Vref @@ -2625,6 +2634,12 @@ ); AGESA_STATUS +AgesaHaltThisAp( + IN UINTN FcnData, + IN AGESA_HALT_THIS_AP_PARAMS *HaltApParams +); + +AGESA_STATUS AgesaHookBeforeDramInit ( IN UINTN SocketIdModuleId, IN OUT MEM_DATA_STRUCT *MemData -- To view, visit https://review.coreboot.org/24999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Gerrit-Change-Number: 24999 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nami: Add WACOM EMR support
by Furquan Shaikh (Code Review) 05 Mar '18

05 Mar '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/24997 ) Change subject: mb/google/poppy/variants/nami: Add WACOM EMR support ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/24997/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/devicetree.cb: https://review.coreboot.org/#/c/24997/1/src/mainboard/google/poppy/variants… PS1, Line 277: GPP_D2 This is not the pen power enable gpio. It is the detect pin. https://review.coreboot.org/#/c/24997/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/gpio.c: https://review.coreboot.org/#/c/24997/1/src/mainboard/google/poppy/variants… PS1, Line 170: 1 Why do you need to take it out of reset here? It should be done by the power resource that you have added in ACPI. -- To view, visit https://review.coreboot.org/24997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbe809a48959e5749262aeb1b89b09c4bdafbbc2 Gerrit-Change-Number: 24997 Gerrit-PatchSet: 1 Gerrit-Owner: Jasper Lee <jasper_lee(a)compal.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jasper Lee <jasper_lee(a)compal.com> Gerrit-Reviewer: Jimmy M Wang <jimmym_wang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 15:07:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy : Get SKU_ID from EC for Nami/Vayne
by Furquan Shaikh (Code Review) 05 Mar '18

05 Mar '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/24996 ) Change subject: mb/google/poppy : Get SKU_ID from EC for Nami/Vayne ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/24996/1/src/mainboard/google/poppy/ramstage… File src/mainboard/google/poppy/ramstage.c: https://review.coreboot.org/#/c/24996/1/src/mainboard/google/poppy/ramstage… PS1, Line 28: board_sku_id This should be moved under mainboard/google/poppy/variants/nami/. https://review.coreboot.org/#/c/24996/1/src/mainboard/google/poppy/ramstage… PS1, Line 48: mainboard_devtree_update Do you intend to do this before FSP-S is run? If yes, then you can add a call in mainboard_silicon_init_params to do variant_silicon_init_params(FSP_SIL_UPD *params) and handle enabling/disabling of ports there. If no, then you can keep the ports enabled in devicetree.cb for nami and handle it in something like mainboard/google/poppy/variants/nami/pl2.c. Though, you will have to rename pl2.c to something like device.c. https://review.coreboot.org/#/c/24996/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/24996/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 105: mainboard_devtree_update There is no need to add a callback from SoC code. This can be handled completely in mainboard/variant-specific code. -- To view, visit https://review.coreboot.org/24996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75 Gerrit-Change-Number: 24996 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jimmy M Wang <jimmym_wang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 15:00:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/soc/amd/stoneyridge: cleanup southbridge.c
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24998 ) Change subject: src/soc/amd/stoneyridge: cleanup southbridge.c ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22707/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68263/ : SUCCESS -- To view, visit https://review.coreboot.org/24998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Gerrit-Change-Number: 24998 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 13:51:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2018