build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23818 )
Change subject: soc/amd/common: Save the UMA settings from AGESA
......................................................................
Patch Set 4: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67826/ : SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/22322/ : SUCCESS
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55
Gerrit-Change-Number: 23818
Gerrit-PatchSet: 4
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Fri, 23 Feb 2018 03:04:29 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: Yes
Hello Zhongze Hu, Shelley Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/23845
to look at the new patch set (#2).
Change subject: fizz: Enable PCIe port 11, 12 on device tree
......................................................................
fizz: Enable PCIe port 11, 12 on device tree
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.
dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector
on fizz to meet the requirement. We also need to enable the ports on device tree.
BUG=b:72523836
TEST=none
BRANCH=fizz
CQ-DEPEND=CL:*571936
Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu(a)google.com>
Tested-by: Zhongze Hu <frankhu(a)google.com>
Reviewed-by: Shelley Chen <shchen(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen(a)chromium.org>
Tested-by: Shelley Chen <shchen(a)chromium.org>
Signed-off-by: Zhongze Hu <frankhu(a)chromium.org>
---
M src/mainboard/google/fizz/devicetree.cb
1 file changed, 28 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/23845/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Icded9850d833752680e0174b6c476e657817b319
Gerrit-Change-Number: 23845
Gerrit-PatchSet: 2
Gerrit-Owner: Zhongze Hu <frankhu(a)chromium.org>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Zhongze Hu <frankhu(a)chromium.org>
Gerrit-Reviewer: Zhongze Hu <frankhu(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/23845 )
Change subject: fizz: Enable PCIe port 11, 12 on device tree
......................................................................
Patch Set 1:
No Signed-off-by line in commit message --> just need to commit with -s option.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Icded9850d833752680e0174b6c476e657817b319
Gerrit-Change-Number: 23845
Gerrit-PatchSet: 1
Gerrit-Owner: Zhongze Hu <frankhu(a)chromium.org>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Zhongze Hu <frankhu(a)chromium.org>
Gerrit-Reviewer: Zhongze Hu <frankhu(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 22 Feb 2018 22:02:42 +0000
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