coreboot-gerrit February 2018

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Change in coreboot[master]: soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17
by Julien Viard de Galbert (Code Review) 23 Feb '18

23 Feb '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23851 Change subject: soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17 ...................................................................... soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17 Rework display_fsp_smbios_memory_info_hob (shared code). Import code to convert memory HOB to dimm info for SMBIOS table 17 mostly copied from fsp1_1 mainboard_save_dimm_info. Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/denverton_ns/chip.c A src/soc/intel/denverton_ns/hob_mem.c A src/soc/intel/denverton_ns/include/soc/hob_mem.h M src/soc/intel/denverton_ns/include/soc/ramstage.h M src/soc/intel/denverton_ns/romstage.c 6 files changed, 271 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/23851/1 diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 5feea13..f137fd1 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -45,6 +45,7 @@ romstage-y += fiamux.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_mem.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += memmap.c @@ -63,6 +64,7 @@ ramstage-y += tsc_freq.c ramstage-y += spi.c ramstage-y += fiamux.c +ramstage-y += hob_mem.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index a43504c..30b4d8c 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -32,6 +32,7 @@ #include <soc/ramstage.h> #include <soc/fiamux.h> #include <spi-generic.h> +#include <soc/hob_mem.h> static void pci_domain_set_resources(device_t dev) { @@ -65,7 +66,11 @@ dev->ops = &cpu_bus_ops; } -static void soc_init(void *data) { fsp_silicon_init(false); } +static void soc_init(void *data) +{ + fsp_silicon_init(false); + soc_save_dimm_info(); +} static void soc_final(void *data) {} diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c new file mode 100644 index 0000000..6a22965 --- /dev/null +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * Copyright (C) 2017-2018 Online SAS. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <string.h> + +#include <soc/hob_mem.h> + +#include <smbios.h> +#include <memory_info.h> + +#if !defined(__PRE_RAM__) +#include <soc/ramstage.h> +#endif + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \ + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \ +} + +static const FSP_SMBIOS_MEMORY_INFO *soc_get_fsp_smbios_memory_info_hob(void) +{ + size_t hob_size; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return NULL; + } + + return memory_info_hob; +} + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +static void soc_display_fsp_smbios_memory_info_hob( + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob) +{ + int channel, dimm; + const DIMM_INFO *dimm_info; + const CHANNEL_INFO *channel_info; + + /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ + printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); + printk(BIOS_DEBUG, " 0x%02x: Revision\n", + memory_info_hob->Revision); + printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", + memory_info_hob->MemoryType); + printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", + memory_info_hob->MemoryFrequencyInMHz); + printk(BIOS_DEBUG, " %d: DataWidth in bits\n", + memory_info_hob->DataWidth); + printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", + memory_info_hob->ErrorCorrectionType); + printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", + memory_info_hob->ChannelCount); + for (channel = 0; channel < memory_info_hob->ChannelCount; + channel++) { + channel_info = &memory_info_hob->ChannelInfo[channel]; + printk(BIOS_DEBUG, " Channel %d\n", channel); + printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", + channel_info->ChannelId); + printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", + channel_info->DimmCount); + for (dimm = 0; dimm < channel_info->DimmCount; + dimm++) { + dimm_info = &channel_info->DimmInfo[dimm]; + printk(BIOS_DEBUG, " DIMM %d\n", dimm); + printk(BIOS_DEBUG, " 0x%02x: DimmId\n", + dimm_info->DimmId); + printk(BIOS_DEBUG, " %d: SizeInMb\n", + dimm_info->SizeInMb); + printk(BIOS_DEBUG, " 0x%04x: MfgId\n", + dimm_info->MfgId); + printk(BIOS_DEBUG, "%*.*s: ModulePartNum\n", + (int)sizeof(dimm_info->ModulePartNum), + (int)sizeof(dimm_info->ModulePartNum), + dimm_info->ModulePartNum); + } + } +} + +void display_fsp_smbios_memory_info_hob(void) +{ + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + /* Get the memory info HOB */ + memory_info_hob = soc_get_fsp_smbios_memory_info_hob(); + + if (memory_info_hob == NULL) + return; + + soc_display_fsp_smbios_memory_info_hob(memory_info_hob); +} +#endif + +#if !defined(__PRE_RAM__) +/* Save the DIMM information for SMBIOS table 17 */ +void soc_save_dimm_info(void) +{ + int channel; + const CHANNEL_INFO *channel_info; + int dimm; + const DIMM_INFO *dimm_info; + int dimm_max; + int index; + struct memory_info *mem_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + /* Get the memory info HOB */ + memory_info_hob = soc_get_fsp_smbios_memory_info_hob(); + + if (memory_info_hob == NULL) + return; + + /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + soc_display_fsp_smbios_memory_info_hob(memory_info_hob); +#endif + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &memory_info_hob->ChannelInfo[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + dimm_info = &channel_info->DimmInfo[dimm]; + + /* Populate the DIMM information */ + if (dimm_info->SizeInMb) { + mem_info->dimm[index].dimm_size = + dimm_info->SizeInMb; + mem_info->dimm[index].ddr_type = + memory_info_hob->MemoryType; + mem_info->dimm[index].ddr_frequency = + memory_info_hob->MemoryFrequencyInMHz; + mem_info->dimm[index].channel_num = + channel_info->ChannelId; + mem_info->dimm[index].dimm_num = + dimm_info->DimmId; + + strncpy( + (char *)mem_info->dimm[index].module_part_number, + (char *)dimm_info->ModulePartNum, 18); + mem_info->dimm[index].mod_id = + dimm_info->MfgId; + switch (memory_info_hob->DataWidth) { + default: + case 8: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_8; + break; + + case 16: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_16; + break; + + case 32: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_32; + break; + + case 64: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_64; + break; + + case 128: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_128; + break; + } + + /* Add any mainboard specific information */ + mainboard_add_dimm_info(mem_info, + channel, dimm, index); + index++; + } + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +/* Add any mainboard specific information */ +__attribute__((weak)) void mainboard_add_dimm_info( + struct memory_info *mem_info, + int channel, int dimm, int index) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +#endif diff --git a/src/soc/intel/denverton_ns/include/soc/hob_mem.h b/src/soc/intel/denverton_ns/include/soc/hob_mem.h new file mode 100644 index 0000000..79711d6 --- /dev/null +++ b/src/soc/intel/denverton_ns/include/soc/hob_mem.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * Copyright (C) 2017-2018 Online SAS. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _DENVERTON_NS_HOB_MEM_H +#define _DENVERTON_NS_HOB_MEM_H + +#include <fsp/util.h> + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +void display_fsp_smbios_memory_info_hob(void); +#endif + +void soc_save_dimm_info(void); + +#endif // _DENVERTON_NS_HOB_MEM_H diff --git a/src/soc/intel/denverton_ns/include/soc/ramstage.h b/src/soc/intel/denverton_ns/include/soc/ramstage.h index 63ed432..d0b6d43 100644 --- a/src/soc/intel/denverton_ns/include/soc/ramstage.h +++ b/src/soc/intel/denverton_ns/include/soc/ramstage.h @@ -20,10 +20,13 @@ #include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/opregion.h> +#include <memory_info.h> void denverton_init_cpus(device_t dev); void mainboard_silicon_init_params(FSPS_UPD *params); void southcluster_enable_dev(device_t dev); +void mainboard_add_dimm_info(struct memory_info *mem_info, int channel, + int dimm, int index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index f675933..4c31110 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -27,77 +27,10 @@ #include <soc/smbus.h> #include <soc/smm.h> #include <soc/soc_util.h> +#include <soc/hob_mem.h> void __attribute__((weak)) mainboard_config_gpios(void) {} -#define FSP_SMBIOS_MEMORY_INFO_GUID \ -{ \ - 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \ - 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \ -} - -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) -static void display_fsp_smbios_memory_info_hob(void) -{ - int channel, dimm; - size_t hob_size; - const DIMM_INFO *dimm_info; - const CHANNEL_INFO *channel_info; - const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; - - /* Locate the memory info HOB */ - memory_info_hob = fsp_find_extension_hob_by_guid( - smbios_memory_info_guid, - &hob_size); - - if (memory_info_hob == NULL || hob_size == 0) { - printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); - return; - } - - /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ - printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); - printk(BIOS_DEBUG, " 0x%02x: Revision\n", - memory_info_hob->Revision); - printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", - memory_info_hob->MemoryType); - printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", - memory_info_hob->MemoryFrequencyInMHz); - printk(BIOS_DEBUG, " %d: DataWidth in bits\n", - memory_info_hob->DataWidth); - printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", - memory_info_hob->ErrorCorrectionType); - printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", - memory_info_hob->ChannelCount); - for (channel = 0; channel < memory_info_hob->ChannelCount; - channel++) { - channel_info = &memory_info_hob->ChannelInfo[channel]; - printk(BIOS_DEBUG, " Channel %d\n", channel); - printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", - channel_info->ChannelId); - printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", - channel_info->DimmCount); - for (dimm = 0; dimm < channel_info->DimmCount; - dimm++) { - dimm_info = &channel_info->DimmInfo[dimm]; - printk(BIOS_DEBUG, " DIMM %d\n", dimm); - printk(BIOS_DEBUG, " 0x%02x: DimmId\n", - dimm_info->DimmId); - printk(BIOS_DEBUG, " %d: SizeInMb\n", - dimm_info->SizeInMb); - printk(BIOS_DEBUG, " 0x%04x: MfgId\n", - dimm_info->MfgId); - printk(BIOS_DEBUG, "%*.*s: ModulePartNum\n", - (int)sizeof(dimm_info->ModulePartNum), - (int)sizeof(dimm_info->ModulePartNum), - dimm_info->ModulePartNum); - } - } -} -#endif - static void early_pmc_init(void) { /* PMC (B0:D31:F2). */ -- To view, visit https://review.coreboot.org/23851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e Gerrit-Change-Number: 23851 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: MAINTAINERS: Update INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Maintai...
by build bot (Jenkins) (Code Review) 23 Feb '18

23 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23847 ) Change subject: MAINTAINERS: Update INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Maintainers ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67835/ : SUCCESS -- To view, visit https://review.coreboot.org/23847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2803af80ac8c2b1d04ecd125c0cb123e736cdf7e Gerrit-Change-Number: 23847 Gerrit-PatchSet: 2 Gerrit-Owner: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Mariusz Szafranski Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 16:52:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [NOT TESTED]mainboard/asus/a8v-e_*: Fix w83627ehg registers
by build bot (Jenkins) (Code Review) 23 Feb '18

23 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23849 ) Change subject: [NOT TESTED]mainboard/asus/a8v-e_*: Fix w83627ehg registers ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67834/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22329/ : SUCCESS -- To view, visit https://review.coreboot.org/23849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If1be087e4b964cb7a782a574f2b9e007c71f8393 Gerrit-Change-Number: 23849 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 09:58:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [NOT TESTED]mainboard/asus/a8v-e_deluxe: Fix w83627ehg registers
by build bot (Jenkins) (Code Review) 23 Feb '18

23 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23849 ) Change subject: [NOT TESTED]mainboard/asus/a8v-e_deluxe: Fix w83627ehg registers ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67833/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22328/ : SUCCESS -- To view, visit https://review.coreboot.org/23849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If1be087e4b964cb7a782a574f2b9e007c71f8393 Gerrit-Change-Number: 23849 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 09:38:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [NOT TESTED]mainboard/asus/a8v-e_deluxe: Fix w83627ehg registers
by Elyes HAOUAS (Code Review) 23 Feb '18

23 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23849 Change subject: [NOT TESTED]mainboard/asus/a8v-e_deluxe: Fix w83627ehg registers ...................................................................... [NOT TESTED]mainboard/asus/a8v-e_deluxe: Fix w83627ehg registers CR 0x24, 0x2a and 0x2c are global control registers. Change-Id: If1be087e4b964cb7a782a574f2b9e007c71f8393 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/a8v-e_deluxe/romstage.c 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/23849/1 diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 5ade055..556884d 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -46,6 +46,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define DUMMY_DEV PNP_DEV(0x2e, 0) void memreset(int controllers, const struct mem_controller *ctrl) { } void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -94,17 +95,17 @@ { u8 reg; - pnp_enter_conf_state(SERIAL_DEV); + pnp_enter_conf_state(DUMMY_DEV); /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + reg = pnp_read_config(DUMMY_DEV, 0x24); + pnp_write_config(DUMMY_DEV, 0x24, (reg & ~0x40)); /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + reg = pnp_read_config(DUMMY_DEV, 0x2a); + pnp_write_config(DUMMY_DEV, 0x2a, (reg | 1)); /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_conf_state(SERIAL_DEV); + reg = pnp_read_config(DUMMY_DEV, 0x2c); + pnp_write_config(DUMMY_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_conf_state(DUMMY_DEV); pnp_enter_conf_state(ACPI_DEV); pnp_set_logical_device(ACPI_DEV); -- To view, visit https://review.coreboot.org/23849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If1be087e4b964cb7a782a574f2b9e007c71f8393 Gerrit-Change-Number: 23849 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: MAINTAINERS: Updated INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Mainta...
by Mariusz Szafranski (Code Review) 23 Feb '18

23 Feb '18

Mariusz Szafranski has posted comments on this change. ( https://review.coreboot.org/23847 ) Change subject: MAINTAINERS: Updated INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Maintainers Added David, Jeff, and Shine Removed Fei ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/23847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2803af80ac8c2b1d04ecd125c0cb123e736cdf7e Gerrit-Change-Number: 23847 Gerrit-PatchSet: 1 Gerrit-Owner: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Mariusz Szafranski Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 08:59:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointer
by build bot (Jenkins) (Code Review) 23 Feb '18

23 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23808 ) Change subject: mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointer ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67832/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22327/ : SUCCESS -- To view, visit https://review.coreboot.org/23808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd Gerrit-Change-Number: 23808 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 05:34:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Refactor northbridge resource allocator
by build bot (Jenkins) (Code Review) 23 Feb '18

23 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23819 ) Change subject: soc/amd/stoneyridge: Refactor northbridge resource allocator ...................................................................... Patch Set 5: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67829/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22325/ : SUCCESS -- To view, visit https://review.coreboot.org/23819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Gerrit-Change-Number: 23819 Gerrit-PatchSet: 5 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 03:12:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: skylake: Fixed acpi UPWE disables usb port unexpectedly
by Kane Chen (Code Review) 23 Feb '18

23 Feb '18

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/23848 Change subject: skylake: Fixed acpi UPWE disables usb port unexpectedly ...................................................................... skylake: Fixed acpi UPWE disables usb port unexpectedly In PORTSC, Port Enabled/Disabled(PED) is RW1CS. When there is a USB device attached on system, current UPWE method will set 1 to PED, this will cause port disabled as it's RW1CS This change is inspired by xhci_port_state_to_neutral in linux xhci driver. It will mask all RO and RWS bits and set WDE and WCE. Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 13 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/23848/1 diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 08f35bc..f967f65 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -29,14 +29,21 @@ /* Map ((XMEM << 16) + Local0 in PSCR */ OperationRegion (PSCR, SystemMemory, Add (ShiftLeft (Arg2, 16), Local0), 0x10) - Field (PSCR, AnyAcc, NoLock, Preserve) + Field (PSCR, DWordAcc, NoLock, Preserve) { - , 25, - UPCE, 1, - UPDE, 1, + PSCT, 32, } - Store (One, UPCE) - Store (One, UPDE) + + Store(PSCT, Local0) + /* + * And port status/control reg with RO and RWS bits + * RO bits: 0, 3, 10:13, 30 + * RWS bits are 5:8, 9, 14:15, 25:27 + */ + And (Local0, 0x4E00FFE9, Local0) + /* Set WCE and WDE bits */ + Or (Local0, 0x6000000, Local0) + Store(Local0, PSCT) } /* -- To view, visit https://review.coreboot.org/23848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Gerrit-Change-Number: 23848 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: soc/amd/common: Save the UMA settings from AGESA
by build bot (Jenkins) (Code Review) 23 Feb '18

23 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23818 ) Change subject: soc/amd/common: Save the UMA settings from AGESA ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67828/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22324/ : SUCCESS -- To view, visit https://review.coreboot.org/23818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Gerrit-Change-Number: 23818 Gerrit-PatchSet: 5 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Feb 2018 03:09:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018