coreboot-gerrit February 2018

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Change in coreboot[master]: fizz: Enable PCIe port 11, 12 on device tree
by Zhongze Hu (Code Review) 22 Feb '18

22 Feb '18

Hello Zhongze Hu, I'd like you to do a code review. Please visit https://review.coreboot.org/23845 to review the following change. Change subject: fizz: Enable PCIe port 11, 12 on device tree ...................................................................... fizz: Enable PCIe port 11, 12 on device tree Our CFM daughter card would like to use individual PCIe lanes for two different devices on the card. dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector on fizz to meet the requirement. We also need to enable the ports on device tree. BUG=b:72523836 TEST=none BRANCH=fizz CQ-DEPEND=CL:*571936 Change-Id: Icded9850d833752680e0174b6c476e657817b319 Reviewed-on: https://chromium-review.googlesource.com/923867 Commit-Ready: Zhongze Hu <frankhu(a)google.com> Tested-by: Zhongze Hu <frankhu(a)google.com> Reviewed-by: Shelley Chen <shchen(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924860 Commit-Queue: Shelley Chen <shchen(a)chromium.org> Tested-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/23845/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 3b084ff..5eeb03c 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -228,6 +228,32 @@ # RP 9 uses uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" + # Enable Root port 11 for BtoB. + register "PcieRpEnable[10]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[10]" = "1" + # RP 11 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[10]" = "2" + # RP 11, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[10]" = "1" + # RP 11, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[10]" = "2" + + # Enable Root port 12 for BtoB. + register "PcieRpEnable[11]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[11]" = "1" + # RP 12 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[11]" = "2" + # RP 12, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[11]" = "1" + # RP 12, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[11]" = "1" + # RP 12 uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[11]" = "2" + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front @@ -351,8 +377,8 @@ end end # PCI Express Port 9 for BtoB device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on -- To view, visit https://review.coreboot.org/23845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icded9850d833752680e0174b6c476e657817b319 Gerrit-Change-Number: 23845 Gerrit-PatchSet: 1 Gerrit-Owner: Zhongze Hu <frankhu(a)chromium.org> Gerrit-Reviewer: Zhongze Hu <frankhu(a)google.com>

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Change in coreboot[master]: src/arch/x86/smbios.c: Fix type 17 part number
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23844 ) Change subject: src/arch/x86/smbios.c: Fix type 17 part number ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67821/ : SUCCESS -- To view, visit https://review.coreboot.org/23844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Gerrit-Change-Number: 23844 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 19:36:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/arch/x86/smbios.c: Fix type 17 part number
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23844 ) Change subject: src/arch/x86/smbios.c: Fix type 17 part number ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67820/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22318/ : SUCCESS -- To view, visit https://review.coreboot.org/23844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Gerrit-Change-Number: 23844 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 19:08:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common/block/pi/amd_late_init.c: Fix part number
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23825 ) Change subject: soc/amd/common/block/pi/amd_late_init.c: Fix part number ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67819/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22317/ : SUCCESS -- To view, visit https://review.coreboot.org/23825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I427262873f9ec80f459245e5f509e28a68de3074 Gerrit-Change-Number: 23825 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 17:50:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/arch/x86/smbios.c: Fix type 17 part number
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23844 ) Change subject: src/arch/x86/smbios.c: Fix type 17 part number ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67818/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22316/ : SUCCESS -- To view, visit https://review.coreboot.org/23844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Gerrit-Change-Number: 23844 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 17:48:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/arch/x86/smbios.c: Fix type 17 part number
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23844 ) Change subject: src/arch/x86/smbios.c: Fix type 17 part number ...................................................................... Patch Set 1: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67817/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22315/ : SUCCESS -- To view, visit https://review.coreboot.org/23844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Gerrit-Change-Number: 23844 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 17:41:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/arch/x86/smbios.c: Fix type 17 part number
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23844 ) Change subject: src/arch/x86/smbios.c: Fix type 17 part number ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67816/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22315/ : SUCCESS -- To view, visit https://review.coreboot.org/23844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Gerrit-Change-Number: 23844 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 17:11:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/arch/x86/smbios.c: Fix type 17 part number
by Richard Spiegel (Code Review) 22 Feb '18

22 Feb '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23844 Change subject: src/arch/x86/smbios.c: Fix type 17 part number ...................................................................... src/arch/x86/smbios.c: Fix type 17 part number Some DIMMs have invalid strings when it comes to part number (bytes 0x149-0x15c). It should be ASCIIZ with unused space filled with white spaces (ASCII 0x20). Byte 20 should be 0, all others should be ASCII. Create a test that detects invalid strings and replace invalid characters with *. If a replacement was made the output string then must be <Invalid (replaced string)>. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Use code to examine SMBIOS, while testing different valid and invalid strings. Remove string injection before committing. Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/arch/x86/smbios.c M src/include/memory_info.h 2 files changed, 41 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/23844/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 548e6ed..e83b739 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -32,6 +32,7 @@ #if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif +#include <soc/southbridge.h> static u8 smbios_checksum(u8 *p, u32 length) { @@ -195,11 +196,34 @@ } } +/* this function will fill the corresponding part number */ +static void smbios_fill_dimm_part_number(char *part_number, + struct smbios_type17 *t) +{ + int i, invalid; + + invalid = 0; /* assume valid*/ + for (i = 0; i < DIMM_INFO_PART_NUMBER_SIZE - 1; i++) { + if (part_number[i] < 0x20) { + invalid = 1; + part_number[i] = '*'; + } + } + if (invalid) { + char string_buffer[256]; + + snprintf(string_buffer, sizeof(string_buffer), "Invalid (%s)", + part_number); + t->part_number = smbios_add_string(t->eos, string_buffer); + } else + t->part_number = smbios_add_string(t->eos, part_number); + +} + static int create_smbios_type17_for_dimm(struct dimm_info *dimm, unsigned long *current, int *handle) { struct smbios_type17 *t = (struct smbios_type17 *)*current; - uint8_t length; char locator[40]; memset(t, 0, sizeof(struct smbios_type17)); @@ -236,8 +260,7 @@ smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t); /* put '\0' in the end of data */ - length = sizeof(dimm->serial); - dimm->serial[length - 1] = '\0'; + dimm->serial[DIMM_INFO_SERIAL_SIZE - 1] = '\0'; if (dimm->serial[0] == 0) t->serial_number = smbios_add_string(t->eos, "None"); else @@ -252,10 +275,8 @@ t->bank_locator = smbios_add_string(t->eos, locator); /* put '\0' in the end of data */ - length = sizeof(dimm->module_part_number); - dimm->module_part_number[length - 1] = '\0'; - t->part_number = smbios_add_string(t->eos, - (const char *)dimm->module_part_number); + dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; + smbios_fill_dimm_part_number((char *)dimm->module_part_number, t); /* Synchronous = 1 */ t->type_detail = 0x0080; @@ -607,13 +628,14 @@ unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; - unsigned long tables; + unsigned long tables, temp; int len = 0; int max_struct_size = 0; int handle = 0; current = ALIGN(current, 16); printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current); + temp = current; se = (struct smbios_entry *)current; current += sizeof(struct smbios_entry); @@ -662,5 +684,7 @@ sizeof(struct smbios_entry) - 0x10); se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); + PrintBuffer(temp, 0x280, "SMBIOS"); + PrintSmbios(temp); return current; } diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 8569ee4..a1b3553 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -19,6 +19,10 @@ #include <stdint.h> #include <compiler.h> +#define DIMM_INFO_SERIAL_SIZE 5 +#define DIMM_INFO_PART_NUMBER_SIZE 19 +#define DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */ + /* * If this table is filled and put in CBMEM, * then these info in CBMEM will be used to generate smbios type 17 table @@ -31,10 +35,10 @@ uint8_t channel_num; uint8_t dimm_num; uint8_t bank_locator; - /* The 5th byte is '\0' for the end of string */ - uint8_t serial[5]; - /* The 19th byte is '\0' for the end of string */ - uint8_t module_part_number[19]; + /* The last byte is '\0' for the end of string */ + uint8_t serial[DIMM_INFO_SERIAL_SIZE]; + /* The last byte is '\0' for the end of string */ + uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE]; uint16_t mod_id; uint8_t mod_type; uint8_t bus_width; @@ -42,8 +46,7 @@ struct memory_info { uint8_t dimm_cnt; - /* Maximum num of dimm is 8 */ - struct dimm_info dimm[8]; + struct dimm_info dimm[DIMM_INFO_TOTAL]; } __packed; #endif -- To view, visit https://review.coreboot.org/23844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Gerrit-Change-Number: 23844 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/kahlee: Use GPIO macros for baseboard
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23830 ) Change subject: mb/google/kahlee: Use GPIO macros for baseboard ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67814/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22313/ : SUCCESS -- To view, visit https://review.coreboot.org/23830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Gerrit-Change-Number: 23830 Gerrit-PatchSet: 5 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 17:03:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: smbios: Extend Baseboard (or Module) Information (type2)
by build bot (Jenkins) (Code Review) 22 Feb '18

22 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23842 ) Change subject: smbios: Extend Baseboard (or Module) Information (type2) ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67811/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22310/ : SUCCESS -- To view, visit https://review.coreboot.org/23842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9fe1c4fe70c66f8a7fcc75b93672421ae808bf1b Gerrit-Change-Number: 23842 Gerrit-PatchSet: 2 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Feb 2018 16:37:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018