coreboot-gerrit February 2018

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Change in coreboot[master]: mainboard/amd/serengeti_cheetah: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23538 Change subject: mainboard/amd/serengeti_cheetah: Fix coding style ...................................................................... mainboard/amd/serengeti_cheetah: Fix coding style Change-Id: I380368873e0508c3a55ac1c4ea0de172e675cf3a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/serengeti_cheetah/acpi_tables.c M src/mainboard/amd/serengeti_cheetah/mptable.c 2 files changed, 29 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/23538/1 diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 41e12eb..d700e1d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -57,7 +57,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=7; } @@ -67,7 +67,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=7; } } @@ -75,9 +75,10 @@ int i; int j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if (!(sysconf.pci1234[i] & 0x1)) + continue; /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: @@ -95,7 +96,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=d; } } @@ -104,7 +105,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=d; } @@ -116,7 +117,7 @@ } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) - current, 0, 0, 2, 5 ); + current, 0, 0, 2, 5); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ @@ -147,16 +148,15 @@ /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ + for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; - if((sysconf.pci1234[i] & 1) != 1 ) continue; + if ((sysconf.pci1234[i] & 1) != 1) + continue; u8 c; - if(i < 7) { + if (i < 7) c = (u8) ('4' + i - 1); - } - else { + else c = (u8) ('A' + i - 1 - 6); - } current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 0210368..9b05fc0 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -49,24 +49,23 @@ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { + if (res) smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res2mmio(res, 0, 0)); - } } dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { + if (res) smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res2mmio(res, 0, 0)); - } } j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; switch(sysconf.hcid[i]) { case 1: /* 8132 */ @@ -74,18 +73,16 @@ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { + if (res) smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res2mmio(res, 0, 0)); - } } dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { + if (res) smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res2mmio(res, 0, 0)); - } } break; } @@ -104,32 +101,29 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); /*Slot 3 PCI 32 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ - } /* Slot 4 PCI 32 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ - } /* Slot 1 PCI-X 133/100/66 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); - } /* Slot 2 PCI-X 133/100/66 */ - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ - } j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for (i = 1; i < sysconf.hc_possible_num; i++) { + if (!(sysconf.pci1234[i] & 0x1)) + continue; int ii; device_t dev; struct resource *res; @@ -141,9 +135,8 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Slot 1 PCI-X 133/100/66 */ - for(ii = 0; ii < 4; ii++) { + for (ii = 0; ii < 4; ii++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); - } } } @@ -152,9 +145,8 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Slot 2 PCI-X 133/100/66 */ - for(ii = 0; ii < 4; ii++) { + for (ii = 0; ii < 4; ii++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */ - } } } -- To view, visit https://review.coreboot.org/23538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I380368873e0508c3a55ac1c4ea0de172e675cf3a Gerrit-Change-Number: 23538 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/msi/ms9652_fam10: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23537 ) Change subject: mainboard/msi/ms9652_fam10: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66902/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21488/ : SUCCESS -- To view, visit https://review.coreboot.org/23537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d6f738d358a0a3d4b602a2a607143d98f4710ed Gerrit-Change-Number: 23537 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:41:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/msi/ms9185: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23536 ) Change subject: mainboard/msi/ms9185: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66901/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21487/ : SUCCESS -- To view, visit https://review.coreboot.org/23536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Gerrit-Change-Number: 23536 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:38:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/msi/ms9652_fam10: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23537 Change subject: mainboard/msi/ms9652_fam10: Fix coding style ...................................................................... mainboard/msi/ms9652_fam10: Fix coding style Change-Id: I8d6f738d358a0a3d4b602a2a607143d98f4710ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/msi/ms9652_fam10/get_bus_conf.c M src/mainboard/msi/ms9652_fam10/mptable.c 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/23537/1 diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 0614e1f..19f8d3b 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -70,7 +70,8 @@ printk(BIOS_SPEW, "get_bus_conf()\n"); - if(get_bus_conf_done == 1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -80,7 +81,7 @@ memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i = 0; i < sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -99,7 +100,7 @@ printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i = 2; i < 8; i++) { + for (i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 7d83c46..6adc53e 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -88,17 +88,16 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j = 7; j >= 2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i = 0; i < 4; i++) { + for (j = 7; j >= 2; j--) { + if (!m->bus_mcp55[j]) + continue; + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } } - for(j = 0; j < 1; j++) - for(i = 0; i < 4; i++) { + for (j = 0; j < 1; j++) + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); -- To view, visit https://review.coreboot.org/23537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8d6f738d358a0a3d4b602a2a607143d98f4710ed Gerrit-Change-Number: 23537 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/msi/ms9282: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23535 ) Change subject: mainboard/msi/ms9282: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66900/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21486/ : SUCCESS -- To view, visit https://review.coreboot.org/23535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6fb31238afff56ff16cf58104f8bed8e9832544c Gerrit-Change-Number: 23535 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:33:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/msi/ms9185: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23536 Change subject: mainboard/msi/ms9185: Fix coding style ...................................................................... mainboard/msi/ms9185: Fix coding style Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/msi/ms9185/mptable.c M src/mainboard/msi/ms9185/romstage.c 2 files changed, 11 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/23536/1 diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index e93602b..e90fd54 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -54,7 +54,7 @@ { device_t dev = 0; struct resource *res; - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -80,9 +80,8 @@ //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // - } @@ -91,7 +90,7 @@ { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { + if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); dword |= (1 << 4); // enable interrupts @@ -101,46 +100,39 @@ //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 // AIC 8130 Galileo Technology... - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // - } //pci slot (on bcm5785) - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); // - } //onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // - } //onboard Broadcom - for(i = 0; i < 2; i++) { + for (i = 0; i < 2; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // - } // First PCI-E x8 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); // - } // Second PCI-E x8 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); // - } // Third PCI-E x1 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); // - } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index a86b57a..e509529 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -181,7 +181,7 @@ #if 0 int i; - for(i = 0; i < 2; i++) { + for (i = 0; i < 2; i++) { activate_spd_rom(sysinfo->ctrl+i); dump_smbus_registers(); } -- To view, visit https://review.coreboot.org/23536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Gerrit-Change-Number: 23536 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/biostar/am1ml: Add required space before opening parenthesi...
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23534 ) Change subject: mainboard/biostar/am1ml: Add required space before opening parenthesis '(' ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66899/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21485/ : SUCCESS -- To view, visit https://review.coreboot.org/23534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1ea93ec54f6ca52e1af8ff09998b8859358b5a0 Gerrit-Change-Number: 23534 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:30:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/msi/ms9282: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23535 Change subject: mainboard/msi/ms9282: Fix coding style ...................................................................... mainboard/msi/ms9282: Fix coding style Change-Id: I6fb31238afff56ff16cf58104f8bed8e9832544c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/msi/ms9282/mptable.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23535/1 diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index 4619737..c53fe78 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -99,17 +99,16 @@ //NIC2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j = 7; j >= 2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i = 0; i < 4; i++) { + for (j = 7; j >= 2; j--) { + if (!m->bus_mcp55[j]) + continue; + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } } - for(j = 0; j < 1; j++) - for(i = 0; i < 4; i++) { + for (j = 0; j < 1; j++) + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); -- To view, visit https://review.coreboot.org/23535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6fb31238afff56ff16cf58104f8bed8e9832544c Gerrit-Change-Number: 23535 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/hp/dl165_g6_fam10: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23533 ) Change subject: mainboard/hp/dl165_g6_fam10: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66898/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21484/ : SUCCESS -- To view, visit https://review.coreboot.org/23533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e3bb9a0e9670fca67016523eac437140ff03188 Gerrit-Change-Number: 23533 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:26:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/biostar/am1ml: Add required space before opening parenthesi...
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23534 Change subject: mainboard/biostar/am1ml: Add required space before opening parenthesis '(' ...................................................................... mainboard/biostar/am1ml: Add required space before opening parenthesis '(' Change-Id: Ic1ea93ec54f6ca52e1af8ff09998b8859358b5a0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/biostar/am1ml/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/23534/1 diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 20708cc..7caa4dc 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -153,7 +153,7 @@ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; - for(i = 0; i < 200000; i++) + for (i = 0; i < 200000; i++) val = inb(0xcd6); outb(0xEA, 0xCD6); -- To view, visit https://review.coreboot.org/23534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic1ea93ec54f6ca52e1af8ff09998b8859358b5a0 Gerrit-Change-Number: 23534 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit February 2018