coreboot-gerrit February 2018

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Change in coreboot[master]: mainboard/hp/dl165_g6_fam10: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23533 Change subject: mainboard/hp/dl165_g6_fam10: Fix coding style ...................................................................... mainboard/hp/dl165_g6_fam10: Fix coding style Change-Id: I3e3bb9a0e9670fca67016523eac437140ff03188 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c M src/mainboard/hp/dl165_g6_fam10/mptable.c 2 files changed, 11 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/23533/1 diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 68c3881..84c7c9b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -69,7 +69,8 @@ int i; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -80,7 +81,7 @@ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i = 0; i < sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -102,28 +103,24 @@ printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1); dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev)); - if(dev) { + if (dev) m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); } /* bcm5780 */ - for(i = 1; i < 6; i++) { + for (i = 1; i < 6; i++) { dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); - if(dev) { + if (dev) m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + else printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1); - } } /*I/O APICs: APIC ID Version State Address*/ apicid_base = 0x10; - for(i = 0; i < 3; i++) + for (i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index b1c91c8..6a27d97 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -58,7 +58,7 @@ device_t dev = 0; int i; struct resource *res; - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -86,7 +86,7 @@ { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { + if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 @@ -129,7 +129,7 @@ { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { + if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); dword |= (1 << 4); // enable interrupts -- To view, visit https://review.coreboot.org/23533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e3bb9a0e9670fca67016523eac437140ff03188 Gerrit-Change-Number: 23533 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/hp/dl145_g3: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23532 ) Change subject: mainboard/hp/dl145_g3: Fix coding style ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66897/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21483/ : SUCCESS -- To view, visit https://review.coreboot.org/23532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Gerrit-Change-Number: 23532 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:19:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp/dl145_g3: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23532 ) Change subject: mainboard/hp/dl145_g3: Fix coding style ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66896/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21482/ : ABORTED -- To view, visit https://review.coreboot.org/23532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Gerrit-Change-Number: 23532 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:13:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp/dl145_g3: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/23532 ) Change subject: mainboard/hp/dl145_g3: Fix coding style ...................................................................... mainboard/hp/dl145_g3: Fix coding style Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/dl145_g3/get_bus_conf.c M src/mainboard/hp/dl145_g3/mptable.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/23532/2 -- To view, visit https://review.coreboot.org/23532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Gerrit-Change-Number: 23532 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/hp/dl145_g3: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23532 Change subject: mainboard/hp/dl145_g3: Fix coding style ...................................................................... mainboard/hp/dl145_g3: Fix coding style Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/dl145_g3/get_bus_conf.c M src/mainboard/hp/dl145_g3/mptable.c 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/23532/1 diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index d69e224..9cbb7ba 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -68,7 +68,8 @@ int i; struct mb_sysconf_t *m; - if(get_bus_conf_done == 1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -78,7 +79,7 @@ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i = 0; i < sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -100,18 +101,17 @@ printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1); dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev)); - if(dev) { + if (dev) m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); } /* bcm5780 */ - for(i = 1; i < 6; i++) { + for (i = 1; i < 6; i++) { dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); - if(dev) { + if (dev) { m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 86affe8..4e33f9b 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -57,7 +57,7 @@ device_t dev = 0; int i; struct resource *res; - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); -- To view, visit https://review.coreboot.org/23532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Gerrit-Change-Number: 23532 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/hp/dl145_g1: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23531 ) Change subject: mainboard/hp/dl145_g1: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66895/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21481/ : SUCCESS -- To view, visit https://review.coreboot.org/23531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f Gerrit-Change-Number: 23531 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:09:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp/dl145_g1: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23531 Change subject: mainboard/hp/dl145_g1: Fix coding style ...................................................................... mainboard/hp/dl145_g1: Fix coding style Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/dl145_g1/acpi_tables.c M src/mainboard/hp/dl145_g1/get_bus_conf.c M src/mainboard/hp/dl145_g1/romstage.c 3 files changed, 14 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/23531/1 diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index 1b4ada1..1084bfb 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -66,9 +66,10 @@ int i; int j = 0; - for(i = 1; i< sysconf.hc_possible_num; i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if (!(sysconf.pci1234[i] & 0x1)) + continue; // 8131 need to use +4 switch (sysconf.hcid[i]) { diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index da02095..7a9e3b5 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -52,7 +52,8 @@ device_t dev; int i; - if(get_bus_conf_done == 1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once get_bus_conf_done = 1; @@ -60,7 +61,7 @@ struct mb_sysconf_t *m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i = 0; i < sysconf.hc_possible_num; i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -75,30 +76,24 @@ /* 8111 */ dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { + if (dev) m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { + else printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); - } /* 8131-1 */ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); - if (dev) { + if (dev) m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { + else printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); - } /* 8131-2 */ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); - if (dev) { + if (dev) m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { + else printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); - } /*I/O APICs: APIC ID Version State Address*/ diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 91f03a7..1ef3658 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -175,12 +175,10 @@ enable_smbus(); int i; - for(i = 0; i < 2; i++) { + for (i = 0; i < 2; i++) activate_spd_rom(&sysinfo->ctrl[i]); - } - for(i = RC0; i <= RC1; i<<=1) { + for (i = RC0; i <= RC1; i <<= 1) change_i2c_mux(i); - } //dump_spd_registers(&sysinfo->ctrl[0]); //dump_spd_registers(&sysinfo->ctrl[1]); -- To view, visit https://review.coreboot.org/23531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f Gerrit-Change-Number: 23531 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/gigabyte/m57sli: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23530 ) Change subject: mainboard/gigabyte/m57sli: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66894/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21480/ : SUCCESS -- To view, visit https://review.coreboot.org/23530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If469989a33b7aaca55503108601fb158f264fc06 Gerrit-Change-Number: 23530 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:01:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/gigabyte/ga_2761gxdk: Remove unnecessary braces {}
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23529 ) Change subject: mainboard/gigabyte/ga_2761gxdk: Remove unnecessary braces {} ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66893/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21479/ : SUCCESS -- To view, visit https://review.coreboot.org/23529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1c7104eb8520f20c826f5936029739a093d4dba Gerrit-Change-Number: 23529 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 07:59:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/gigabyte/m57sli: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23530 Change subject: mainboard/gigabyte/m57sli: Fix coding style ...................................................................... mainboard/gigabyte/m57sli: Fix coding style Change-Id: If469989a33b7aaca55503108601fb158f264fc06 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/m57sli/mptable.c 1 file changed, 20 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/23530/1 diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 019a7f5..e0af483 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -49,7 +49,7 @@ device_t dev; struct resource *res; - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { @@ -72,22 +72,23 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin)) - PCI_INT(0,sbdn+1,1, 10); /* SMBus */ - PCI_INT(0,sbdn+2,0, 22); /* USB */ - PCI_INT(0,sbdn+2,1, 23); /* USB */ - PCI_INT(0,sbdn+4,0, 21); /* IDE */ - PCI_INT(0,sbdn+5,0, 20); /* SATA */ - PCI_INT(0,sbdn+5,1, 21); /* SATA */ - PCI_INT(0,sbdn+5,2, 22); /* SATA */ - PCI_INT(0,sbdn+6,1, 23); /* HD Audio */ - PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */ + PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */ + PCI_INT(0, sbdn + 2, 0, 22); /* USB */ + PCI_INT(0, sbdn + 2, 1, 23); /* USB */ + PCI_INT(0, sbdn + 4, 0, 21); /* IDE */ + PCI_INT(0, sbdn + 5, 0, 20); /* SATA */ + PCI_INT(0, sbdn + 5, 1, 21); /* SATA */ + PCI_INT(0, sbdn + 5, 2, 22); /* SATA */ + PCI_INT(0, sbdn + 6, 1, 23); /* HD Audio */ + PCI_INT(0, sbdn + 8, 0, 20); /* GBit Ethernet */ /* The PCIe slots, each on its own bus */ k = 1; - for(i = 0; i < 4; i++){ - for(j = 7; j > 1; j--){ - if(k > 3) k = 0; - PCI_INT(j,0,i, 16+k); + for (i = 0; i < 4; i++) { + for (j = 7; j > 1; j--) { + if (k > 3) + k = 0; + PCI_INT(j, 0, i, 16 + k); k++; } k--; @@ -98,10 +99,11 @@ * FireWire is j = 10 */ k = 2; - for(i = 0; i < 4; i++){ - for(j = 6; j < 11; j++){ - if(k > 3) k = 0; - PCI_INT(1,j,i, 16+k); + for (i = 0; i < 4; i++) { + for (j = 6; j < 11; j++) { + if (k > 3) + k = 0; + PCI_INT(1, j, i, 16 + k); k++; } } -- To view, visit https://review.coreboot.org/23530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If469989a33b7aaca55503108601fb158f264fc06 Gerrit-Change-Number: 23530 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit February 2018