coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

1 participants
1573 discussions

Change in coreboot[master]: Fizz: Get OEM ID and SKU ID from EC
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23548 ) Change subject: Fizz: Get OEM ID and SKU ID from EC ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66908/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21493/ : SUCCESS -- To view, visit https://review.coreboot.org/23548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Gerrit-Change-Number: 23548 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 16:04:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Fizz: Get OEM ID and SKU ID from EC
by Daisuke Nojiri (Code Review) 01 Feb '18

01 Feb '18

Daisuke Nojiri has uploaded a new patch set (#2). ( https://review.coreboot.org/23548 ) Change subject: Fizz: Get OEM ID and SKU ID from EC ...................................................................... Fizz: Get OEM ID and SKU ID from EC This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails, it falls back to GPIO pins. Devices with an invalid or uninitialized EEPROM will keep reading from GPIOs because EC_CMD_GET_CROS_BOARD_INFO returns error. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/mainboard/google/fizz/mainboard.c 4 files changed, 145 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/23548/2 -- To view, visit https://review.coreboot.org/23548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Gerrit-Change-Number: 23548 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

1 0

Change in coreboot[master]: Fizz: Get OEM ID and SKU ID from EC
by Daisuke Nojiri (Code Review) 01 Feb '18

01 Feb '18

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/23548 Change subject: Fizz: Get OEM ID and SKU ID from EC ...................................................................... Fizz: Get OEM ID and SKU ID from EC This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails, it falls back to GPIO pins. Devices with an invalid or uninitialized EEPROM will keep reading from GPIOs because EC_CMD_GET_CROS_BOARD_INFO returns error. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M 3rdparty/blobs M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/mainboard/google/fizz/mainboard.c 5 files changed, 146 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/23548/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index a5efee5..d2e558a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit a5efee5fdea55f398decc9cabebce3744bbd8147 +Subproject commit d2e558a81f95f7b9149bea6b8362bb43ade82584 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 89241da..3f81716 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -558,6 +558,40 @@ return google_chromeec_command(&cec_cmd); } +static int cbi_get_uint32(uint32_t *id, uint32_t type) +{ + struct chromeec_command cmd; + struct ec_params_get_cbi p; + uint32_t r; + int rv; + + p.type = type; + + cmd.cmd_code = EC_CMD_GET_CROS_BOARD_INFO; + cmd.cmd_version = 0; + cmd.cmd_data_in = &p; + cmd.cmd_data_out = &r; + cmd.cmd_size_in = sizeof(p); + cmd.cmd_size_out = sizeof(r); + cmd.cmd_dev_index = 0; + + rv = google_chromeec_command(&cmd); + if (rv < 0) + return rv; + *id = r; + return 0; +} + +int google_chromeec_get_sku_id2(uint32_t *id) +{ + return cbi_get_uint32(id, CBI_DATA_SKU_ID); +} + +int google_chromeec_get_oem_id(uint32_t *id) +{ + return cbi_get_uint32(id, CBI_DATA_OEM_ID); +} + #ifndef __SMM__ u16 google_chromeec_get_board_version(void) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 90bb6fa..7192315 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -64,6 +64,15 @@ success, < 0 otherwise. */ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags); +/** + * Get OEM (or SKU) ID from EC + * + * @param id [OUT] oem/sku id + * @return 0 on success or negative integer for errors. + */ +int google_chromeec_get_oem_id(uint32_t *id); +int google_chromeec_get_sku_id2(uint32_t *id); + /* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */ #define MEC_EMI_BASE 0x800 #define MEC_EMI_SIZE 8 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 92fb2a8..a8d6b30 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -4363,6 +4363,66 @@ uint32_t action; }; +/* Run verification on a slot */ +#define EC_CMD_EFS_VERIFY 0x011E + +struct __ec_align1 ec_params_efs_verify { + uint8_t region; /* enum ec_flash_region */ +}; + +/* + * Retrieve info from Cros Board Info store. Response is based on the data + * type. Integers return a uint32. Strings return a string, using the response + * size to determine how big it is. + */ +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +/* + * Write info into Cros Board Info on EEPROM. Write fails if the board has + * hardware write-protect enabled. + */ +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 + +enum cbi_data_type { + /* integer types */ + CBI_DATA_BOARD_VERSION = 0, + CBI_DATA_OEM_ID = 1, + CBI_DATA_SKU_ID = 2, + /* string types */ + CBI_FIRST_STRING_PARAM = 0x1000, + CBI_DATA_COUNT, +}; + +/* + * Flags to control read operation + * + * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify + * write was successful without reboot. + */ +#define CBI_GET_RELOAD (1 << 0) + +struct __ec_align4 ec_params_get_cbi { + uint32_t type; /* enum cbi_data_type */ + uint32_t flag; /* CBI_GET_* */ +}; + +/* + * Flags to control write behavior. + * + * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's + * useful when writing multiple fields in a row. + * INIT: Need to be set when creating a new CBI from scratch. All fields + * will be initialized to zero first. + */ +#define CBI_SET_NO_SYNC (1 << 0) +#define CBI_SET_INIT (1 << 1) + +struct __ec_align1 ec_params_set_cbi { + uint32_t type; /* enum cbi_data_type */ + uint32_t flag; /* CBI_SET_* */ + uint32_t data; /* For numeric value */ + uint8_t raw[]; /* For string and raw data */ +}; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 3a8aa54..343785c 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -86,21 +86,32 @@ BJ_90W_19V, BJ_90W_19V, BJ_65W_19V }, }; -static const char *oem_id = "GOOGLE"; -static const char *oem_table_id = "FIZZ"; - -static uint8_t board_sku_id(void) +static uint8_t read_sku_id_from_gpio(void) { - static int id = -1; const gpio_t sku_id_gpios[] = { GPIO_SKU_ID0, GPIO_SKU_ID1, GPIO_SKU_ID2, GPIO_SKU_ID3, }; - if (id < 0) - id = gpio_base2_value(sku_id_gpios, ARRAY_SIZE(sku_id_gpios)); - return id; + return gpio_base2_value(sku_id_gpios, ARRAY_SIZE(sku_id_gpios)); +} + +static uint8_t board_sku_id(void) +{ + static int sku_id = -1; + + if (sku_id < 0) { + uint32_t id; + if (google_chromeec_get_sku_id2(&id)) + /* TODO: Once transition completes, raise error instead + * of returning gpio value which could be unintended. */ + /* No caching if it's read from GPIO. */ + return read_sku_id_from_gpio(); + sku_id = id; + } + + return sku_id; } /* @@ -162,17 +173,31 @@ *psyspl2_val = SET_PSYSPL2(psyspl2); } -static uint8_t board_oem_id(void) +static uint8_t read_oem_id_from_gpio(void) { - static int id = -1; const gpio_t oem_id_gpios[] = { GPIO_OEM_ID1, GPIO_OEM_ID2, GPIO_OEM_ID3, }; - if (id < 0) - id = gpio_base2_value(oem_id_gpios, ARRAY_SIZE(oem_id_gpios)); - return id; + return gpio_base2_value(oem_id_gpios, ARRAY_SIZE(oem_id_gpios)); +} + +static uint8_t board_oem_id(void) +{ + static int oem_id = -1; + + if (oem_id < 0) { + uint32_t id; + if (google_chromeec_get_oem_id(&id)) + /* TODO: Once transition completes, raise error instead + * of returning gpio value which could be unintended. */ + /* No caching if it's read from GPIO. */ + return read_oem_id_from_gpio(); + oem_id = id; + } + + return oem_id; } const char *smbios_mainboard_sku(void) @@ -192,6 +217,8 @@ static unsigned long mainboard_write_acpi_tables( device_t device, unsigned long current, acpi_rsdp_t *rsdp) { + const char *oem_id = "GOOGLE"; + const char *oem_table_id = "FIZZ"; uintptr_t start_addr; uintptr_t end_addr; struct nhlt *nhlt; @@ -227,8 +254,9 @@ uint8_t sku = board_sku_id(); enum bj_adapter bj; + printk(BIOS_INFO, "OEM:%u(0x%x) SKU:%u(0x%x)\n", oem, oem, sku, sku); if (oem >= OEM_ID_COUNT || sku >= SKU_ID_COUNT) { - printk(BIOS_ERR, "Unrecognized OEM or SKU: %d/%d\n", oem, sku); + printk(BIOS_ERR, "Unrecognized OEM or SKU\n"); return; } -- To view, visit https://review.coreboot.org/23548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Gerrit-Change-Number: 23548 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

1 0

Change in coreboot[master]: mb/google/nautilus: To work around the power issue of MIPI and USB ca...
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23546 ) Change subject: mb/google/nautilus: To work around the power issue of MIPI and USB cameras ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66905/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21491/ : SUCCESS -- To view, visit https://review.coreboot.org/23546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28 Gerrit-Change-Number: 23546 Gerrit-PatchSet: 1 Gerrit-Owner: Andy Yeh <andy.yeh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 16:03:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23547 ) Change subject: vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9 ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66906/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21492/ : SUCCESS -- To view, visit https://review.coreboot.org/23547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f Gerrit-Change-Number: 23547 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 16:01:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9
by Marc Jones (Code Review) 01 Feb '18

01 Feb '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/23547 Change subject: vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9 ...................................................................... vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9 Update the shared AGESA headers to 1.3.0.9. This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated to the same version. Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/AGESA.h M src/vendorcode/amd/pi/00670F00/AMD.h M src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h M src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h M src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h M src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h 9 files changed, 89 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/23547/1 diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h index 09a1680..17f6986 100644 --- a/src/vendorcode/amd/pi/00670F00/AGESA.h +++ b/src/vendorcode/amd/pi/00670F00/AGESA.h @@ -13,7 +13,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -1800,6 +1800,14 @@ } DEVICE_BLOCK_HEADER; ///=============================================================================== +/// CPU_VREF_OVERRIDE +/// +typedef struct _CPU_VREF_OVERRIDE{ + IN UINT8 VrefOp; ///< Operater to adjust VrefHspeed + IN UINT8 VrefOffset; ///< Offset to adjust VrefHspeed +} CPU_VREF_OVERRIDE; + +///=============================================================================== /// MEM_PARAMETER_STRUCT /// This data structure is used to pass wrapper parameters to the memory configuration code /// @@ -2116,6 +2124,8 @@ ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} IN UINT16 CustomVddioSupport; ///< CustomVddioSupport ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE} + IN CPU_VREF_OVERRIDE CpuVrefOverride[2][4]; ///< Structure to adjust VrefHspeed + ///< PerDct, Per MemPstate } MEM_PARAMETER_STRUCT; @@ -2858,6 +2868,7 @@ IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround + IN BOOLEAN CfgFchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update } FCH_PLATFORM_POLICY; @@ -2993,7 +3004,7 @@ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} - IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy + IN CONST FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy IN BOOLEAN CfgIommuSupport; ///< IOMMU support IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing @@ -3087,6 +3098,7 @@ IN BOOLEAN CfgAcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING} IN BOOLEAN CfgSmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING} IN BOOLEAN CfgSmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR} + IN UINT16 CfgBootUpDisplayDevice; ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE} IN BOOLEAN Reserved; ///< reserved... } BUILD_OPT_CFG; @@ -3171,6 +3183,9 @@ IN BOOLEAN AcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING} IN BOOLEAN SmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING} IN BOOLEAN SmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR} + IN UINT16 BootUpDisplayDevice; ///< The boot up display device selected. + ///< If equal to 0 default setting in VBIOS for boot up display devices + ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE} } PLATFORM_CONFIGURATION; @@ -3404,6 +3419,7 @@ OUT UINT8 Channel:2; ///< Channel ID OUT UINT8 Dimm:2; ///< DIMM ID OUT UINT8 DimmPresent:1; ///< Dimm Present + OUT BOOLEAN Interleaved; ///< Interleaved; OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range ///< of memory mapped to the referenced Memory Device. OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with diff --git a/src/vendorcode/amd/pi/00670F00/AMD.h b/src/vendorcode/amd/pi/00670F00/AMD.h index c4d56c9..483ee32 100644 --- a/src/vendorcode/amd/pi/00670F00/AMD.h +++ b/src/vendorcode/amd/pi/00670F00/AMD.h @@ -13,7 +13,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,12 +45,8 @@ #ifndef _AMD_H_ #define _AMD_H_ -#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8) -#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h)) - #define AGESA_REVISION "Arch2008" -#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00} +#define AGESA_ID "AGESA" // // @@ -58,8 +54,11 @@ // // #define LAST_ENTRY 0xFFFFFFFFul +#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) #define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +/* coreboot binaryPI - start */ #define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D') +/* coreboot binaryPI - end */ #define IOCF8 0xCF8 #define IOCFC 0xCFC @@ -130,37 +129,27 @@ /// AGESA struct name typedef enum { // AGESA BASIC FUNCTIONS - AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle - AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle - AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle - AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle - AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle - AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle - AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle - AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle - AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle - AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle - AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle - AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle - AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle - AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle - AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle - AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle - AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle - AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle - AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle - AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, - AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, - FCH_INIT_RESET = 0x00040000, - FCH_INIT_ENV = 0x00041000, - FCH_INIT_MID = 0x00042000, - FCH_INIT_LATE = 0x00043000, - FCH_INIT_S3_EARLY_RESTORE = 0x00044000, - FCH_INIT_S3_LATE_RESTORE = 0x00045000, - AMD_SET_VALUE_invalid = 0x00081000, - AMD_GET_VALUE_invalid = 0x00082000 + AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle + AMD_CREATE_STRUCT, ///< AmdCreateStruct handle + AMD_INIT_EARLY, ///< AmdInitEarly entry point handle + AMD_INIT_ENV, ///< AmdInitEnv entry point handle + AMD_INIT_LATE, ///< AmdInitLate entry point handle + AMD_INIT_MID, ///< AmdInitMid entry point handle + AMD_INIT_POST, ///< AmdInitPost entry point handle + AMD_INIT_RESET, ///< AmdInitReset entry point handle + AMD_INIT_RESUME, ///< AmdInitResume entry point handle + AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle + AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle + AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle + AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle + AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle + AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle + AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle + AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h index 75169cb..1d53990 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h @@ -14,7 +14,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -656,7 +656,7 @@ */ typedef struct { REGISTER_TABLE_TIME_POINT TimePoint; ///< Time point - CONST REGISTER_TABLE** TableList; ///< The table list. + CONST REGISTER_TABLE* CONST * CONST TableList; ///< The table list. } REGISTER_TABLE_AT_GIVEN_TP; /*------------------------------------------------------------------------------------------*/ /* diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h index f4ffd49..9331cd1 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h @@ -13,7 +13,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -164,7 +164,7 @@ * */ typedef AGESA_STATUS F_CPU_DISABLE_PSTATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN UINT8 StateNumber, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -185,7 +185,7 @@ * */ typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN UINT8 StateNumber, IN BOOLEAN WaitForChange, IN AMD_CONFIG_PARAMS *StdHeader @@ -210,7 +210,7 @@ * */ typedef BOOLEAN F_CPU_GET_IDD_MAX ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN UINT8 StateNumber, OUT UINT32 *ProcIddMax, IN AMD_CONFIG_PARAMS *StdHeader @@ -231,7 +231,7 @@ * */ typedef AGESA_STATUS F_CPU_GET_TSC_RATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES * FamilySpecificServices, OUT UINT32 *FreqInMHz, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -252,7 +252,7 @@ * @retval AGESA_SUCCESS FreqInMHz is valid. */ typedef AGESA_STATUS F_CPU_GET_NB_FREQ ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, OUT UINT32 *FreqInMHz, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -276,7 +276,7 @@ * @retval AGESA_STATUS Northbridge frequency is valid */ typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PLATFORM_CONFIGURATION *PlatformConfig, IN PCI_ADDR *PciAddress, OUT UINT32 *MinFreqInMHz, @@ -306,7 +306,7 @@ * @retval FALSE NbPstate is disabled or invalid */ typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PLATFORM_CONFIGURATION *PlatformConfig, IN PCI_ADDR *PciAddress, IN UINT32 NbPstate, @@ -333,7 +333,7 @@ * */ typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PCI_ADDR *PciAddress, OUT BOOLEAN *NbVidUpdateAll, IN AMD_CONFIG_PARAMS *StdHeader @@ -358,7 +358,7 @@ * */ typedef BOOLEAN F_CPU_GET_NB_IDD_MAX ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN UINT8 StateNumber, OUT UINT32 *NbIddMax, IN AMD_CONFIG_PARAMS *StdHeader @@ -381,7 +381,7 @@ * @retval FALSE The core was previously launched, or has a problem. */ typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN UINT32 CoreNumber, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -401,7 +401,7 @@ * @return One-based number of physical cores on current processor */ typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -420,7 +420,7 @@ * @return The AP's unique core number */ typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -449,7 +449,7 @@ * @retval CoreIdPositionOne Core Id is low */ typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -468,7 +468,7 @@ * */ typedef VOID (F_CPU_SET_WARM_RESET_FLAG) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN AMD_CONFIG_PARAMS *StdHeader, IN WARM_RESET_REQUEST *Request ); @@ -488,7 +488,7 @@ * */ typedef VOID (F_CPU_GET_WARM_RESET_FLAG) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN AMD_CONFIG_PARAMS *StdHeader, OUT WARM_RESET_REQUEST *Request ); @@ -509,7 +509,7 @@ * */ typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, OUT CONST VOID **FamilySpecificArray, OUT UINT8 *NumberOfElements, IN AMD_CONFIG_PARAMS *StdHeader @@ -530,7 +530,7 @@ * */ typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN OUT PLATFORM_FEATS *FeaturesUnion, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -552,7 +552,7 @@ * @retval FALSE The NB PState feature is not enabled. */ typedef BOOLEAN F_IS_NB_PSTATE_ENABLED ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -571,7 +571,7 @@ * */ typedef REGISTER_TABLE_AT_GIVEN_TP *F_GET_REGISTER_TABLE_LIST ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilyServices, IN AMD_CONFIG_PARAMS *StdHeader ); /// Reference to a Method. @@ -590,7 +590,7 @@ * */ typedef F_FAM_SPECIFIC_WORKAROUND **F_GET_WORKAROUND_TABLE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilyServices, OUT UINT16 *NumberOfWorkaroundTableEntries, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -614,7 +614,7 @@ * */ typedef VOID F_PERFORM_EARLY_INIT_ON_CORE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilyServices, IN AMD_CPU_EARLY_PARAMS *EarlyParams, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -644,7 +644,7 @@ * */ typedef VOID F_GET_EARLY_INIT_TABLE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilyServices, OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, IN AMD_CPU_EARLY_PARAMS *EarlyParams, IN AMD_CONFIG_PARAMS *StdHeader @@ -853,7 +853,7 @@ */ VOID GetEmptyArray ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices, OUT CONST VOID **Empty, OUT UINT8 *NumberOfElements, IN AMD_CONFIG_PARAMS *StdHeader diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h index 4d10b42..46906a8 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h @@ -14,7 +14,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -236,7 +236,7 @@ /// Logical CPU ID Table typedef struct { IN UINT32 Elements; ///< Number of Elements - IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer + IN CONST CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer } LOGICAL_ID_TABLE; // MSRs diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h index 46e5b17..21f73a3 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h @@ -14,7 +14,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -937,6 +937,7 @@ UINT32 FchCpuId; ///< Saving CpuId for FCH Module. BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function ) FCH_CS FchCsSupport; ///< FCH Cs function structure + BOOLEAN FchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update } FCH_MISC; @@ -1405,7 +1406,7 @@ ///PTUSBTxStructure typedef struct { PT_USB31Tx USB31Tx[2]; ///< USB31Tx setting -PT_USB30Tx USB30Tx[3]; ///< USB30Tx setting +PT_USB30Tx USB30Tx[6]; ///< USB30Tx setting UINT8 USB20B2Tx00; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[0] UINT8 USB20B2Tx05; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[5] UINT8 USB20B3Tx1113; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[13][11] diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h index 45453a8..c80dc52 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h @@ -14,7 +14,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -81,6 +81,7 @@ BOOLEAN FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader); BOOLEAN FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader); UINT64 FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchInitResetRequest (IN AMD_CONFIG_PARAMS *StdHeader); /// /// Fch Ab Routines diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h index 304ed23..04784fe 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h @@ -14,7 +14,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -115,6 +115,6 @@ #include "FchBiosRamUsage.h" #include "AmdFch.h" -extern BUILD_OPT_CFG UserOptions; +extern CONST BUILD_OPT_CFG UserOptions; #endif // _FCH_PLATFORM_H_ diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h b/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h index 016d822..5811eb0 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h @@ -13,7 +13,7 @@ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -87,6 +87,8 @@ * IDSOPT_PERF_ANALYSIS * IDSOPT_ASSERT_ENABLED * IDS_DEBUG_PORT + * IDS_DEBUG_PORT_SIZE_IN_BYTES + * IDS_DEBUG_TP_PREFIX * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED * IDSOPT_DEBUG_CODE_ENABLED * IDSOPT_IDT_EXCEPTION_TRAP @@ -94,12 +96,10 @@ * **/ - - -//#include "Ids.h" - #define IDSOPT_ERROR_TRAP_ENABLED FALSE +#define IDS_MMAP_SERIAL_PORT + #ifdef DEBUG #define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_CONTROL_ENABLED FALSE @@ -109,12 +109,17 @@ #undef IDS_DEBUG_PRINT_MASK #endif #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_ALL | GFX_MISC | CPU_TRACE_ALL | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT) +#ifdef IDS_MMAP_SERIAL_PORT +#define IDSOPT_SERIAL_PORT 0xfedc6000 +#else #define IDSOPT_SERIAL_PORT 0x3F8 +#endif #define IDSOPT_HEAP_CHECKING TRUE #define IDSOPT_TRACE_BLD_CFG TRUE #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE #define IDSOPT_DEBUG_CODE_ENABLED TRUE #define IDSOPT_C_OPTIMIZATION_DISABLED TRUE +//#define IDSOPT_ASSERT_ENABLED TRUE #else #define IDSOPT_IDS_ENABLED FALSE //#define IDSOPT_ERROR_TRAP_ENABLED FALSE -- To view, visit https://review.coreboot.org/23547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f Gerrit-Change-Number: 23547 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

1 0

Change in coreboot[master]: mb/google/nautilus: To work around the power issue of MIPI and USB ca...
by Andy Yeh (Code Review) 01 Feb '18

01 Feb '18

Andy Yeh has uploaded this change for review. ( https://review.coreboot.org/23546 Change subject: mb/google/nautilus: To work around the power issue of MIPI and USB cameras ...................................................................... mb/google/nautilus: To work around the power issue of MIPI and USB cameras On EVT, the USB and MIPI cameras share the same power source; as a result, when the MIPI camera driver turns of the camera, USB camera is turned off as well. For USB cameras to work on EVT devices we will need a hack in coreboot to leave the camera power always-on. This power issue will be fixed on DVT build. Will revert this patch once confirmed power source could be supplied standalone. BUG=b:72616688 TEST: Verified the MIPI and USB camera function on DUT board Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28 Signed-off-by: Andy Yeh <andy.yeh(a)intel.com> --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/23546/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5eaf5b7..2b97043 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -39,7 +39,13 @@ Method (PMOF, 0, Serialized) { /* Make Sure all PMIC outputs are off. */ If (LEqual (VSIC, Zero)) { + /* + * On Nautilus Pre-EVT/EVT, the USB and MIPI share the same power source, + * before HW fix in DVT, temporarily disabled turn off 3V3_VDD + */ +#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_NAUTILUS) CTXS(EN_PP3300_DX_CAM) +#endif } } -- To view, visit https://review.coreboot.org/23546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28 Gerrit-Change-Number: 23546 Gerrit-PatchSet: 1 Gerrit-Owner: Andy Yeh <andy.yeh(a)intel.corp-partner.google.com>

1 0

Change in coreboot[master]: mainboard/amd/olivehillplus: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23539 ) Change subject: mainboard/amd/olivehillplus: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66904/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21490/ : SUCCESS -- To view, visit https://review.coreboot.org/23539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I489780d205e0784914063454c6071b046df6cc30 Gerrit-Change-Number: 23539 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 09:02:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/amd/serengeti_cheetah: Fix coding style
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23538 ) Change subject: mainboard/amd/serengeti_cheetah: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66903/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21489/ : SUCCESS -- To view, visit https://review.coreboot.org/23538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I380368873e0508c3a55ac1c4ea0de172e675cf3a Gerrit-Change-Number: 23538 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 08:56:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/amd/olivehillplus: Fix coding style
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23539 Change subject: mainboard/amd/olivehillplus: Fix coding style ...................................................................... mainboard/amd/olivehillplus: Fix coding style Change-Id: I489780d205e0784914063454c6071b046df6cc30 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/olivehillplus/romstage.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/23539/1 diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index ff2c4c4..4ad0f6d 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -72,7 +72,8 @@ */ { int i; - for(i = 0; i < 200000; i++) inb(0xCD6); + for (i = 0; i < 200000; i++) + inb(0xCD6); } post_code(0x37); -- To view, visit https://review.coreboot.org/23539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I489780d205e0784914063454c6071b046df6cc30 Gerrit-Change-Number: 23539 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2018