coreboot-gerrit February 2018

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Change in coreboot[master]: mainboard/gigabyte/ga_2761gxdk: Remove unnecessary braces {}
by Elyes HAOUAS (Code Review) 01 Feb '18

01 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23529 Change subject: mainboard/gigabyte/ga_2761gxdk: Remove unnecessary braces {} ...................................................................... mainboard/gigabyte/ga_2761gxdk: Remove unnecessary braces {} Fix coding style Change-Id: Id1c7104eb8520f20c826f5936029739a093d4dba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/ga_2761gxdk/mptable.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/23529/1 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 1544205..991f24e 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -88,17 +88,16 @@ PCI_INT(0, sbdn+5, 2, 0x15); // 21 PCI_INT(0, sbdn+8, 0, 0x16); // 22 - for(j = 7; j >= 2; j--) { - if(!bus_sis966[j]) continue; - for(i = 0; i < 4; i++) { + for (j = 7; j >= 2; j--) { + if (!bus_sis966[j]) + continue; + for (i = 0; i < 4; i++) PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); - } } - for(j = 0; j < 2; j++) - for(i = 0; i < 4; i++) { + for (j = 0; j < 2; j++) + for (i = 0; i < 4; i++) PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); - } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); -- To view, visit https://review.coreboot.org/23529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id1c7104eb8520f20c826f5936029739a093d4dba Gerrit-Change-Number: 23529 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/winent: Remove unnecessary braces {}
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23524 ) Change subject: mainboard/winent: Remove unnecessary braces {} ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66892/ : SUCCESS -- To view, visit https://review.coreboot.org/23524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48a7bd4bd98d1a9d7b0ce4c12e09284fa4be6c7a Gerrit-Change-Number: 23524 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 07:32:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/broadcom/blast: Remove unnecessary braces {}
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23523 ) Change subject: mainboard/broadcom/blast: Remove unnecessary braces {} ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66891/ : SUCCESS -- To view, visit https://review.coreboot.org/23523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d Gerrit-Change-Number: 23523 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 07:29:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/inteltool: Add Pentium 4 model f6x.
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23521 ) Change subject: util/inteltool: Add Pentium 4 model f6x. ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66890/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21478/ : SUCCESS -- To view, visit https://review.coreboot.org/23521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c Gerrit-Change-Number: 23521 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 07:25:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Set PsysPl3 and Pl4
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23527 ) Change subject: soc/intel/skylake: Set PsysPl3 and Pl4 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66888/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21476/ : SUCCESS -- To view, visit https://review.coreboot.org/23527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Gerrit-Change-Number: 23527 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 06:39:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/fizz: Determine PsysPl3 and Pl4 values
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23528 ) Change subject: google/fizz: Determine PsysPl3 and Pl4 values ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66889/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21477/ : SUCCESS -- To view, visit https://review.coreboot.org/23528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Gerrit-Change-Number: 23528 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 06:38:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/fizz: Determine PsysPl3 and Pl4 values
by Shelley Chen (Code Review) 01 Feb '18

01 Feb '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/23528 Change subject: google/fizz: Determine PsysPl3 and Pl4 values ...................................................................... google/fizz: Determine PsysPl3 and Pl4 values Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid brownouts. BUG=b:71594855 BRANCH=None TEST=Boot and check MSRs for appropriate values Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/mainboard.c 1 file changed, 32 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23528/1 diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 3a8aa54..93cd8e5 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -108,28 +108,33 @@ * * Set Pl2 and SysPl2 values based on detected charger. * If detected barrel jack, use values below based on SKU. - * +-------------+-----+---------+-----+------+------+ - * | sku_id | PL2 | PsysPL2 | PL4 | Pmax | Prop | - * +-------------+-----+---------+-----+------+------+ - * | i7 U42 | 44 | 81 | 71 | 120 | 48 | - * | i5 U42 | 44 | 81 | 71 | 120 | 48 | - * | i3 U42 | 44 | 81 | 71 | 120 | 48 | - * | i7 U22 | 29 | 58 | 43 | 91 | 48 | - * | i5 U22 | 29 | 58 | 43 | 91 | 48 | - * | i3 U22 | 29 | 58 | 43 | 91 | 48 | - * | celeron U22 | 29 | 58 | 43 | 91 | 48 | - * +-------------+-----+---------+-----+------+------+ + * definitions: + * x = no value entered. Use default value in parenthesis. + * will set 0 to anything that shouldn't be set. + * n = max value of power adapter. + * +-------------+-----+---------+-----------+-------+------+------+ + * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | Pmax | Prop | + * +-------------+-----+---------+-----------+-------+------+------+ + * | i7 U42 | 44 | 81 | x(.85PL4) | x(77) | 120 | 48 | + * | i5 U42 | 44 | 81 | x(.85PL4) | x(77) | 120 | 48 | + * | i3 U42 | 44 | 81 | x(.85PL4) | x(77) | 120 | 48 | + * | i7 U22 | 29 | 58 | x(.85PL4) | x(43) | 91 | 48 | + * | i5 U22 | 29 | 58 | x(.85PL4) | x(43) | 91 | 48 | + * | i3 U22 | 29 | 58 | x(.85PL4) | x(43) | 91 | 48 | + * | celeron U22 | 29 | 58 | x(.85PL4) | x(43) | 91 | 48 | + * +-------------+-----+---------+-----------+-------+------+------+ * For USB C charger: - * +-------------+-----+---------+-----+------+------+ - * | Max Power(W)| PL2 | PsysPL2 | PL4 | Pmax | Prop | - * +-------------+-----+---------+-----+------+------+ - * | 60 (U42) | 44 | 54 | 54 | 120 | 48 | - * | 60 (U22) | 29 | 54 | 43 | 91 | 48 | - * | X (U42) | 44 | .9X | .9X | 120 | 48 | - * | X (U22) | 29 | .9X | .9X | 91 | 48 | - * +-------------+-----+---------+-----+------+------+ + * +-------------+-----+---------+---------+-------+------+------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | Pmax | Prop | + * +-------------+-----+---------+---------+-------+------+------+ + * | 60 (U42) | 44 | 54 | 54 | 54 | 120 | 48 | + * | 60 (U22) | 29 | 54 | 54 | x(43) | 91 | 48 | + * | n (U42) | 44 | .9n | .9n | .9n | 120 | 48 | + * | n (U22) | 29 | .9n | .9n | .9n | 91 | 48 | + * +-------------+-----+---------+---------+-------+------+------+ */ -static void mainboard_set_power_limits(u32 *pl2_val, u32 *psyspl2_val) +static void mainboard_set_power_limits(u32 *pl2_val, u32 *psyspl2_val, + u32 *psyspl3_val, u32 *pl4_val) { enum usb_chg_type type; u32 watts; @@ -144,6 +149,7 @@ pl2 = FIZZ_PL2_U22; if ((1 << sku) & u42_mask) pl2 = FIZZ_PL2_U42; + *psyspl3_val = *pl4_val = 0; /* If we can't get charger info or not PD charger, assume barrel jack */ if (rv != 0 || type != USB_CHG_TYPE_PD) { @@ -153,8 +159,11 @@ if ((1 << sku) & u42_mask) psyspl2 = FIZZ_PSYSPL2_U42; } else { - /* Base on max value of adapter */ + /* Detected TypeC. Base on max value of adapter */ psyspl2 = watts; + *psyspl3_val = SET_PSYSPL2(psyspl2); + if ((1 << sku) & u42_mask) + *pl4_val = SET_PSYSPL2(psyspl2); } *pl2_val = pl2; @@ -250,7 +259,8 @@ device_t root = SA_DEV_ROOT; config_t *conf = root->chip_info; - mainboard_set_power_limits(&conf->tdp_pl2_override, &conf->tdp_psyspl2); + mainboard_set_power_limits(&conf->tdp_pl2_override, &conf->tdp_psyspl2, + &conf->tdp_psyspl3, &conf->tdp_pl4); set_bj_adapter_limit(); -- To view, visit https://review.coreboot.org/23528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Gerrit-Change-Number: 23528 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Set PsysPl3 and Pl4
by Shelley Chen (Code Review) 01 Feb '18

01 Feb '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/23527 Change subject: soc/intel/skylake: Set PsysPl3 and Pl4 ...................................................................... soc/intel/skylake: Set PsysPl3 and Pl4 If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/msr.h 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23527/1 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 45f201c..7aa81f0 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -114,6 +114,8 @@ #define PKG_POWER_LIMIT_CLAMP (1 << 16) #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK (0x7f) +#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 +#define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4e8cb81..6568701 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -100,6 +100,12 @@ /* SysPL2 Value in Watts */ u32 tdp_psyspl2; + /* SysPL3 Value in Watts */ + u32 tdp_psyspl3; + + /* PL4 Value in Watts */ + u32 tdp_pl4; + /* * The following fields come from FspUpdVpd.h. * These are configuration values that are passed to FSP during diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 291a40d..f3da826 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -191,6 +191,36 @@ wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); } + /* Set PsysPl3 */ + if (conf->tdp_psyspl3) { + limit = rdmsr(MSR_PL3_CONTROL); + limit.lo = 0; + printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", + conf->tdp_psyspl3); + limit.lo |= (conf->tdp_psyspl3 * power_unit) & + PKG_POWER_LIMIT_MASK; + /* Enable PsysPl3 */ + limit.lo |= PKG_POWER_LIMIT_EN; + /* set max possible time window */ + limit.lo |= PKG_POWER_LIMIT_TIME_MASK << + PKG_POWER_LIMIT_TIME_SHIFT; + /* set minimum duty cycle */ + limit.lo |= PKG_POWER_LIMIT_DUTYCYCLE_MASK << + PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; + wrmsr(MSR_PL3_CONTROL, limit); + } + + /* Set Pl4 */ + if (conf->tdp_pl4) { + limit = rdmsr(MSR_VR_CURRENT_CONFIG); + limit.lo = 0; + printk(BIOS_DEBUG, "CPU PsysPL4 = %u Watts\n", + conf->tdp_pl4); + limit.lo |= (conf->tdp_pl4 * power_unit) & + PKG_POWER_LIMIT_MASK; + wrmsr(MSR_VR_CURRENT_CONFIG, limit); + } + /* Set DDR RAPL power limit by copying from MMIO to MSR */ msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 0bd7f3c..780f94f 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -36,6 +36,7 @@ #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 +#define MSR_PL3_CONTROL 0x615 #define MSR_VR_MISC_CONFIG2 0x636 #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 -- To view, visit https://review.coreboot.org/23527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Gerrit-Change-Number: 23527 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wake
by build bot (Jenkins) (Code Review) 01 Feb '18

01 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23526 ) Change subject: mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wake ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66887/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21475/ : SUCCESS -- To view, visit https://review.coreboot.org/23526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b Gerrit-Change-Number: 23526 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Feb 2018 05:56:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wake
by Furquan Shaikh (Code Review) 01 Feb '18

01 Feb '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/23526 ) Change subject: mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wake ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/23526/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/23526/1//COMMIT_MSG@14 PS1, Line 14: TEST Did you verify that wake over wlan works using this new pin? https://review.coreboot.org/#/c/23526/1//COMMIT_MSG@15 PS1, Line 15: Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> Blank line before Signed-off-by line. -- To view, visit https://review.coreboot.org/23526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b Gerrit-Change-Number: 23526 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 01 Feb 2018 05:51:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit February 2018