build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23546 )
Change subject: mb/google/nautilus: To work around the power issue of MIPI and USB cameras
......................................................................
Patch Set 2: Verified+1
Build Successful
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Matthias Kaehlcke has posted comments on this change. ( https://review.coreboot.org/23561 )
Change subject: google/scarlet: Innolux P097PFG panel use new version initial code
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Verified to be working on dru.
Matches the kernel sequence from https://crosreview.com/890565
LGTM besides the comments on the commit message.
https://review.coreboot.org/#/c/23561/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/23561/1//COMMIT_MSG@7
PS1, Line 7: google/scarlet: Innolux P097PFG panel use new version initial code
:
: There is artifact line in the lower third of the display with now
: initial code. So update this initial code to fix this issue.
You could also mention that this is a sequence provided by Innolux, as opposed to the register dump hack that we merged initially.
https://review.coreboot.org/#/c/23561/1//COMMIT_MSG@12
PS1, Line 12: BUG=b:69689064, b:72191820
: BRANCH=gru
: TEST=boot on dru with an Innolux panel and artifact line disappear.
I'm not really familiar with coreboot upstream work, but I suppose these Chrome OS specific tags are meaningless here.
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Change subject: google/scarlet: Innolux P097PFG panel use new version initial code
......................................................................
Patch Set 1: Verified+1
Build Successful
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Lin Huang has removed Philip Chen from this change. ( https://review.coreboot.org/23561 )
Change subject: google/scarlet: Innolux P097PFG panel use new version initial code
......................................................................
Removed reviewer Philip Chen.
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Hello Bora Guvendik, Sathyanarayana Nujella, Hannah Williams, Lijian Zhao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/23560
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Increase heap size
......................................................................
soc/intel/cannonlake: Increase heap size
After adding NHLT and max98373 amp support, cnlrvp fails to boot
with error: out of memory (free_mem_ptr >= free_mem_end_ptr).
Increase HEAP_SIZE from 0x4000 to 0x8000.
BUG=None
TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp
and verify cnlrvp boots to kernel.
Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/23560/2
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