coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

1 participants
1573 discussions

Change in coreboot[master]: google/lars, lili: Update SPD Data
by Matt DeVillier (Code Review) 02 Feb '18

02 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23569 Change subject: google/lars,lili: Update SPD Data ...................................................................... google/lars,lili: Update SPD Data Combination of several commits from Chromium tree: 3b875a2 [Lars: Update Memory ID for DVT board] b6d7c63 [Lili: Update Memory IDs] f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD] a6571bf [Lili: Update Memory IDs] 80e1841 [Lili: Update Memory IDs] 58d4487 [Lili: Fix memory string show error in spd data] These commits bring lars' SPD data in line with the Chromium tree. Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084 Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39 Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991 Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Signed-off-by: Ren Kuo <Ren.Kuo(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)google.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Tested-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/lars/spd/Makefile.inc A src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex A src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex A src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex A src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex M src/mainboard/google/lars/spd/spd.c M src/mainboard/google/lars/spd/spd.h 7 files changed, 76 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/23569/1 diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc index d6d789e..b6e4fd7 100644 --- a/src/mainboard/google/lars/spd/Makefile.inc +++ b/src/mainboard/google/lars/spd/Makefile.inc @@ -24,13 +24,13 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0011 Single Channel 2GB SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0100 Single Channel 4GB SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b0101 Dual Channel 8GB -SPD_SOURCES += empty # 0b0110 -SPD_SOURCES += empty # 0b0111 -SPD_SOURCES += empty # 0b1000 -SPD_SOURCES += empty # 0b1001 -SPD_SOURCES += empty # 0b1010 -SPD_SOURCES += empty # 0b1011 -SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0110 Dual Channel 4GB +SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866 # 0b0111 Single Channel 4GB +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b1000 Dual Channel 4GB +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1001 Dual Channel 8GB +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866 # 0b1010 Dual Channel 4GB +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1011 Single Channel 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel 4GB SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex new file mode 100644 index 0000000..5c1332e --- /dev/null +++ b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 47 54 41 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex new file mode 100644 index 0000000..7c7c8d2 --- /dev/null +++ b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4A 54 41 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex b/src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex new file mode 100644 index 0000000..8694a40 --- /dev/null +++ b/src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 10 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 75 8C +4D 54 35 32 4C 32 35 36 4D 33 32 44 31 50 46 31 +30 37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex b/src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex new file mode 100644 index 0000000..b059375 --- /dev/null +++ b/src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 21 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 3D 51 +4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 31 +30 37 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c index 106eb83..d9fe579 100644 --- a/src/mainboard/google/lars/spd/spd.c +++ b/src/mainboard/google/lars/spd/spd.c @@ -106,7 +106,8 @@ memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN); if (spd_index != MEM_SINGLE_CHAN0 && spd_index != MEM_SINGLE_CHAN3 - && spd_index != MEM_SINGLE_CHAN4) { + && spd_index != MEM_SINGLE_CHAN4 && spd_index != MEM_SINGLE_CHAN7 + && spd_index != MEM_SINGLE_CHANB && spd_index != MEM_SINGLE_CHANC) { memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN); printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n"); } diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h index d71487b..25cce5e 100644 --- a/src/mainboard/google/lars/spd/spd.h +++ b/src/mainboard/google/lars/spd/spd.h @@ -33,4 +33,7 @@ #define MEM_SINGLE_CHAN0 0x0 #define MEM_SINGLE_CHAN3 0x3 #define MEM_SINGLE_CHAN4 0x4 +#define MEM_SINGLE_CHAN7 0x7 +#define MEM_SINGLE_CHANB 0xb +#define MEM_SINGLE_CHANC 0xc #endif -- To view, visit https://review.coreboot.org/23569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4 Gerrit-Change-Number: 23569 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/lars: Add sdmode-delay property for max98357a
by Matt DeVillier (Code Review) 02 Feb '18

02 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23568 Change subject: google/lars: Add sdmode-delay property for max98357a ...................................................................... google/lars: Add sdmode-delay property for max98357a Adapted from Chromium commit: af3ec09 [Lars: Add sdmode-delay device property for maxim98357a] Add "sdmode-delay" as a device property for the maxim98357a codec. This speaker amp requires both SFRM & BCLK to active and stable before it is unmuted. If there is a BCLK and no SFRM, that results in a pop noise. Adding a configurable delay parameter for all Skylake platforms to allow sufficient time for the BCLK & SFRM on I2S to be stable before the amp unmutes itself to avoid a pop noise at the start of playback. Setting the delay to 5ms since the observed delay between SFRM and unmuting of the amp is around 2ms. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/lars/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/23568/1 diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 64f2a61..344d4b7 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -284,6 +284,7 @@ device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "sdmode_delay" = "5" device generic 0 on end end end # Intel HDA -- To view, visit https://review.coreboot.org/23568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b Gerrit-Change-Number: 23568 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/lars, lili: Set new thermal parameters
by Matt DeVillier (Code Review) 02 Feb '18

02 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23566 Change subject: google/lars,lili: Set new thermal parameters ...................................................................... google/lars,lili: Set new thermal parameters Cherry-pick from Chromium: 55c0eb3 [Lili: Set new thermal parameters] Set new parameters of DPTF for both Lars and Lili. The acoustic will have higher 1.6dB in transition mode, when using Lili fan table on Lars. Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)google.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/lars/acpi/dptf.asl 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/23566/1 diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index 5738fd1..c85e1b6 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -16,28 +16,28 @@ #define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 77 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 70 -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 66 -#define DPTF_TSR0_CRITICAL 71 -#define DPTF_TSR0_ACTIVE_AC0 120 -#define DPTF_TSR0_ACTIVE_AC1 110 -#define DPTF_TSR0_ACTIVE_AC2 47 -#define DPTF_TSR0_ACTIVE_AC3 44 -#define DPTF_TSR0_ACTIVE_AC4 41 -#define DPTF_TSR0_ACTIVE_AC5 38 -#define DPTF_TSR0_ACTIVE_AC6 35 +#define DPTF_TSR0_SENSOR_ID 2 +#define DPTF_TSR0_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_ACTIVE_AC0 60 +#define DPTF_TSR0_ACTIVE_AC1 48 +#define DPTF_TSR0_ACTIVE_AC2 42 +#define DPTF_TSR0_ACTIVE_AC3 39 +#define DPTF_TSR0_ACTIVE_AC4 36 +#define DPTF_TSR0_ACTIVE_AC5 34 +#define DPTF_TSR0_ACTIVE_AC6 32 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 75 -#define DPTF_TSR1_CRITICAL 80 +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 70 -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_SENSOR_ID 0 +#define DPTF_TSR2_SENSOR_NAME "TMP432_Internal" #define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_CRITICAL 70 @@ -83,12 +83,12 @@ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 0, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38, - 37, 0, 0, 0 + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 90, 75, 62, 55, 47, + 41, 0, 0, 0 } }) #endif -- To view, visit https://review.coreboot.org/23566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0 Gerrit-Change-Number: 23566 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com>

1 0

Change in coreboot[master]: google/lars: update device properties for Nuvoton codec
by Matt DeVillier (Code Review) 02 Feb '18

02 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23567 Change subject: google/lars: update device properties for Nuvoton codec ...................................................................... google/lars: update device properties for Nuvoton codec Adapted from Chromium commit: 848ee3a [Lars: Add device properties for Nuvoton codec] Update sar-threshold, sar-compare-time, sar-sampling-time properties to match values in lars' Chromium branch. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/lars/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23567/1 diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 99522cb..64f2a61 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -233,14 +233,14 @@ register "vref_impedance" = "2" # 125kOhm register "micbias_voltage" = "6" # 2.754 register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0a" - register "sar_threshold[1]" = "0x14" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" register "sar_threshold[2]" = "0x26" register "sar_threshold[3]" = "0x73" register "sar_hysteresis" = "0" register "sar_voltage" = "6" - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us register "short_key_debounce" = "3" # 30ms register "jack_insert_debounce" = "7" # 512ms register "jack_eject_debounce" = "0" -- To view, visit https://review.coreboot.org/23567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3 Gerrit-Change-Number: 23567 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/lars: Update DPTF setting
by Matt DeVillier (Code Review) 02 Feb '18

02 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23565 Change subject: google/lars: Update DPTF setting ...................................................................... google/lars: Update DPTF setting Cherry-pick from Chromium: dff141b [Lars: Update DPTF setting] Original-Change-Id: I1f2686eced07c7fb1bde3c660df6d6efac607695 Original-Signed-off-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ifd3e844688588b6d1c69459f75c0d7da93ba3688 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/lars/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/23565/1 diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index 82a23f8..5738fd1 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -125,8 +125,8 @@ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 25000, /* PowerLimitMinimum */ + 25000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */ -- To view, visit https://review.coreboot.org/23565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd3e844688588b6d1c69459f75c0d7da93ba3688 Gerrit-Change-Number: 23565 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com>

1 0

Change in coreboot[master]: mb/lenovo/w520: Add ThinkPad W520 support
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23564 ) Change subject: mb/lenovo/w520: Add ThinkPad W520 support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66963/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21539/ : SUCCESS -- To view, visit https://review.coreboot.org/23564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Gerrit-Change-Number: 23564 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Rikken <nico(a)nicorikken.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 18:44:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/fizz: Get OEM ID and SKU ID from EC
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23548 ) Change subject: mb/google/fizz: Get OEM ID and SKU ID from EC ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66962/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21538/ : SUCCESS -- To view, visit https://review.coreboot.org/23548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Gerrit-Change-Number: 23548 Gerrit-PatchSet: 8 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 18:29:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/lenovo/w520: Add ThinkPad W520 support
by Nico Rikken (Code Review) 02 Feb '18

02 Feb '18

Nico Rikken has uploaded this change for review. ( https://review.coreboot.org/23564 Change subject: mb/lenovo/w520: Add ThinkPad W520 support ...................................................................... mb/lenovo/w520: Add ThinkPad W520 support Tested and working: * 4 RAM-slots * Booting GNU Linux from USB using SeaBios * Speakers * PCIe Wifi * Camera * Fan * Touchpad, trackpoint and keyboard * Ethernet * Keyboard ACPI events Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Signed-off-by: Nico Rikken <nico(a)nicorikken.eu> --- M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/romstage.c A src/mainboard/lenovo/w520/Kconfig A src/mainboard/lenovo/w520/Kconfig.name A src/mainboard/lenovo/w520/board_info.txt 5 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/23564/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 8c19c62..7a7f5fd 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T520 +if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index d6e5edd..6985065 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -99,8 +99,15 @@ }; void mainboard_get_spd(spd_raw_data *spd, bool id_only) { +#if IS_ENABLED(CONFIG_BOARD_LENOVO_T520) read_spd (&spd[0], 0x50, id_only); read_spd (&spd[2], 0x51, id_only); +#elif IS_ENABLED(CONFIG_BOARD_LENOVO_W520) + read_spd (&spd[0], 0x50, id_only); + read_spd (&spd[1], 0x52, id_only); + read_spd (&spd[2], 0x51, id_only); + read_spd (&spd[3], 0x53, id_only); +#endif } void mainboard_early_init(int s3resume) diff --git a/src/mainboard/lenovo/w520/Kconfig b/src/mainboard/lenovo/w520/Kconfig new file mode 100644 index 0000000..87af127 --- /dev/null +++ b/src/mainboard/lenovo/w520/Kconfig @@ -0,0 +1,7 @@ +if BOARD_LENOVO_W520 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad W520" + +endif # BOARD_LENOVO_W520 diff --git a/src/mainboard/lenovo/w520/Kconfig.name b/src/mainboard/lenovo/w520/Kconfig.name new file mode 100644 index 0000000..6f1439e --- /dev/null +++ b/src/mainboard/lenovo/w520/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_W520 + bool "ThinkPad W520" diff --git a/src/mainboard/lenovo/w520/board_info.txt b/src/mainboard/lenovo/w520/board_info.txt new file mode 100644 index 0000000..99f059f --- /dev/null +++ b/src/mainboard/lenovo/w520/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 +Clone of: lenovo/t520 -- To view, visit https://review.coreboot.org/23564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Gerrit-Change-Number: 23564 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Rikken <nico(a)nicorikken.eu>

1 0

Change in coreboot[master]: ec/google/chromeec: Remove wake flag from keyboard IRQ
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23563 ) Change subject: ec/google/chromeec: Remove wake flag from keyboard IRQ ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66961/ : SUCCESS -- To view, visit https://review.coreboot.org/23563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I26e27de68095f8d176108f39312338522d7cfba0 Gerrit-Change-Number: 23563 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 18:26:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: ec/google/chromeec: Remove wake flag from keyboard IRQ
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23563 ) Change subject: ec/google/chromeec: Remove wake flag from keyboard IRQ ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66960/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21537/ : ABORTED -- To view, visit https://review.coreboot.org/23563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I26e27de68095f8d176108f39312338522d7cfba0 Gerrit-Change-Number: 23563 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 18:21:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2018