coreboot-gerrit February 2018

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 44: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67994/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22472/ : SUCCESS -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 44 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 16:49:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/qualcomm/sdm845: Support for new SoC
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24882 ) Change subject: src/soc/qualcomm/sdm845: Support for new SoC ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67992/ : SUCCESS -- To view, visit https://review.coreboot.org/24882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I89c72bebb8597e879db273c3234bf8a84a0aa23b Gerrit-Change-Number: 24882 Gerrit-PatchSet: 2 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Feb 2018 16:23:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 43: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67993/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22471/ : SUCCESS -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 43 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 16:23:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/qualcomm/sdm845: Support for new SoC
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24882 ) Change subject: src/soc/qualcomm/sdm845: Support for new SoC ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67991/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22470/ : SUCCESS -- To view, visit https://review.coreboot.org/24882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I89c72bebb8597e879db273c3234bf8a84a0aa23b Gerrit-Change-Number: 24882 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Feb 2018 15:43:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/qualcomm/sdm845: Support for new SoC
by T.Michael Turney (Code Review) 27 Feb '18

27 Feb '18

T.Michael Turney has uploaded this change for review. ( https://review.coreboot.org/24882 Change subject: src/soc/qualcomm/sdm845: Support for new SoC ...................................................................... src/soc/qualcomm/sdm845: Support for new SoC Change-Id: I89c72bebb8597e879db273c3234bf8a84a0aa23b --- A src/soc/qualcomm/sdm845/Kconfig A src/soc/qualcomm/sdm845/Makefile.inc A src/soc/qualcomm/sdm845/cbmem.c A src/soc/qualcomm/sdm845/i2c.c A src/soc/qualcomm/sdm845/include/soc/gpio.h A src/soc/qualcomm/sdm845/include/soc/memlayout.ld A src/soc/qualcomm/sdm845/soc.c A src/soc/qualcomm/sdm845/spi.c A src/soc/qualcomm/sdm845/timer.c 9 files changed, 313 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/24882/1 diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig new file mode 100644 index 0000000..747052e --- /dev/null +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_QUALCOMM_SDM845 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + +if SOC_QUALCOMM_SDM845 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc new file mode 100644 index 0000000..881ae2f --- /dev/null +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y) + +################################################################################ +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += i2c.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c +verstage-y += i2c.c + +################################################################################ +romstage-y += timer.c +romstage-y += spi.c +romstage-y += i2c.c +romstage-y += cbmem.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += i2c.c +ramstage-y += cbmem.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c new file mode 100644 index 0000000..45cda8f --- /dev/null +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return NULL; +} diff --git a/src/soc/qualcomm/sdm845/i2c.c b/src/soc/qualcomm/sdm845/i2c.c new file mode 100644 index 0000000..8ce6f54 --- /dev/null +++ b/src/soc/qualcomm/sdm845/i2c.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/i2c_simple.h> + +int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, + int seg_count) +{ + return 0; +} diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h new file mode 100644 index 0000000..9b2a0f4 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_ +#define _SOC_QUALCOMM_SDM845_GPIO_H_ + +#include <types.h> + +typedef u32 gpio_t; + +#endif // _SOC_QUALCOMM_SDM845_GPIO_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld new file mode 100644 index 0000000..11a4b5d --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +#define SRAM2_START(addr) SYMBOL(sram2, addr) +#define SRAM2_END(addr) SYMBOL(esram2, addr) + +SECTIONS +{ + SRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 95K) + SRAM_END(0x1469FC00) + + SRAM2_START(0x14816000) + BOOTBLOCK(0x14816000, 32K) + TTB(0x1481E000, 64K) + VBOOT2_WORK(0x1482E000, 16K) + STACK(0x14832000, 16K) + TIMESTAMP(0x14836000, 1K) + PRERAM_CBMEM_CONSOLE(0x14836400, 32K) + PRERAM_CBFS_CACHE(0x1483E400, 70K) + REGION(qclib, 0x1484FC00, 1217K, 0x100) + SRAM2_END(0x14980000) + + DRAM_START(0x80000000) + RAMSTAGE(0x80800000, 128K) + SYMBOL(memlayout_cbmem_top, 0xA1000000) + POSTRAM_CBFS_CACHE(0xA1000000, 384K) +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c new file mode 100644 index 0000000..9f2fbc4 --- /dev/null +++ b/src/soc/qualcomm/sdm845/soc.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void soc_read_resources(device_t dev) +{ + +} + +static void soc_init(device_t dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sdm845_ops = { + CHIP_NAME("SOC Qualcomm SDM845") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c new file mode 100644 index 0000000..175b6cf --- /dev/null +++ b/src/soc/qualcomm/sdm845/spi.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + return 0; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + return 0; +} + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c new file mode 100644 index 0000000..b1df161 --- /dev/null +++ b/src/soc/qualcomm/sdm845/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <delay.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + +} + +void init_timer(void) +{ + +} -- To view, visit https://review.coreboot.org/24882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I89c72bebb8597e879db273c3234bf8a84a0aa23b Gerrit-Change-Number: 24882 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com>

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 42: (3 comments) https://review.coreboot.org/#/c/22374/25/src/drivers/intel/fsp2_0/memory_in… File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/#/c/22374/25/src/drivers/intel/fsp2_0/memory_in… PS25, Line 38: __attribute__((weak)) void mrc_cache_update_hash(const uint8_t *data, > Done Does not compute build issues https://review.coreboot.org/#/c/22374/39/src/drivers/intel/fsp2_0/memory_in… File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/#/c/22374/39/src/drivers/intel/fsp2_0/memory_in… PS39, Line 38: __attribute__((weak)) void mrc_cache_update_hash(const uint8_t *data, > I assume you're planning to add other methods to store the MRC hash? Otherwise, using a weak functio […] Yep that was my idea. https://review.coreboot.org/#/c/22374/39/src/security/tpm/Kconfig File src/security/tpm/Kconfig: https://review.coreboot.org/#/c/22374/39/src/security/tpm/Kconfig@18 PS39, Line 18: > And now that I think of it, I don't think it really make sense to let the user decide between TPM-1. […] Now we have both options. User mode for pluggable TPMs and board mode. -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 42 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 14:43:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/...
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23881 ) Change subject: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/Blue/Bruce/Astronaut ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67990/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22469/ : SUCCESS -- To view, visit https://review.coreboot.org/23881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I401905685cc3078df657919b162272c3de320296 Gerrit-Change-Number: 23881 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 12:44:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/...
by Pan Sheng-Liang (Code Review) 27 Feb '18

27 Feb '18

Pan Sheng-Liang has uploaded this change for review. ( https://review.coreboot.org/23881 Change subject: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/Blue/Bruce/Astronaut ...................................................................... mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/Blue/Bruce/Astronaut Due to there are some chances USB devices can not be detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I401905685cc3078df657919b162272c3de320296 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan(a)quantatw.com> --- M src/mainboard/google/reef/variants/coral/mainboard.c 1 file changed, 56 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/23881/1 diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index a45afc7..97c4c0e 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -19,7 +19,6 @@ #include <soc/cpu.h> #include <soc/intel/apollolake/chip.h> #include <soc/intel/common/vbt.h> -#include <soc/gpio.h> enum { SKU_0_ASTRONAUT = 0, @@ -28,8 +27,13 @@ SKU_3_SANTA = 3, SKU_4_LAVA = 4, SKU_5_LAVA = 5, + SKU_6_BLUE = 6, + SKU_7_BLUE = 7, + SKU_8_BRUCE = 8, SKU_9_LAVA = 9, SKU_10_LAVA = 10, + SKU_11_BRUCE = 11, + SKU_12_BLUE = 12, SKU_61_ASTRONAUT = 61, SKU_62_ASTRONAUT = 62, SKU_160_NASHER = 160, @@ -71,25 +75,63 @@ switch (sku_id) { case SKU_0_ASTRONAUT: case SKU_1_ASTRONAUT: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 2; - break; + case SKU_61_ASTRONAUT: + case SKU_62_ASTRONAUT: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; case SKU_2_SANTA: case SKU_3_SANTA: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 2; - break; + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; case SKU_4_LAVA: case SKU_5_LAVA: case SKU_9_LAVA: case SKU_10_LAVA: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 2; - break; - case SKU_61_ASTRONAUT: - case SKU_62_ASTRONAUT: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 5; + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; + case SKU_6_BLUE: + case SKU_7_BLUE: + case SKU_12_BLUE: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; + case SKU_8_BRUCE: + case SKU_11_BRUCE: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; break; default: break; @@ -101,14 +143,6 @@ int sku_id = variant_board_sku(); switch (sku_id) { - case SKU_0_ASTRONAUT: - case SKU_1_ASTRONAUT: - return "vbt-astronaut.bin"; - break; - case SKU_2_SANTA: - case SKU_3_SANTA: - return "vbt-santa.bin"; - break; case SKU_160_NASHER: case SKU_161_NASHER: case SKU_162_NASHER: @@ -123,34 +157,3 @@ break; } } - -static const struct pad_config nasher_gpio_tables[] = { - /* AVS_DMIC_CLK_A1 */ - PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, Tx1RXDCRx0), - /* AVS_DMIC_CLK_B1 */ - PAD_CFG_NF_IOSSTATE(GPIO_80, NATIVE, DEEP, NF1, Tx1RXDCRx0), -}; - -const struct pad_config *variant_sku_gpio_table(size_t *num) -{ - int sku_id = variant_board_sku(); - const struct pad_config *board_gpio_tables; - - switch (sku_id) { - case SKU_160_NASHER: - case SKU_161_NASHER: - case SKU_162_NASHER: - case SKU_163_NASHER360: - case SKU_164_NASHER360: - case SKU_165_NASHER360: - case SKU_166_NASHER360: - *num = ARRAY_SIZE(nasher_gpio_tables); - board_gpio_tables = nasher_gpio_tables; - break; - default: - *num = 0; - board_gpio_tables = NULL; - break; - } - return board_gpio_tables; -} -- To view, visit https://review.coreboot.org/23881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I401905685cc3078df657919b162272c3de320296 Gerrit-Change-Number: 23881 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com>

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/...
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23880 ) Change subject: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/Blue/Bruce/Astronaut ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67989/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22468/ : SUCCESS -- To view, visit https://review.coreboot.org/23880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I045c14ef87a5920666dc06c2b53f0fed0b702d0e Gerrit-Change-Number: 23880 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 12:34:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/...
by Pan Sheng-Liang (Code Review) 27 Feb '18

27 Feb '18

Pan Sheng-Liang has uploaded this change for review. ( https://review.coreboot.org/23880 Change subject: mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/Blue/Bruce/Astronaut ...................................................................... mainboard/google/coral: Add USB2 phy setting override for Sante/Lava/Blue/Bruce/Astronaut Due to there are some chances USB devices can not be detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I045c14ef87a5920666dc06c2b53f0fed0b702d0e Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan(a)quantatw.com> --- M src/mainboard/google/reef/variants/coral/mainboard.c 1 file changed, 68 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23880/1 diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index 853276e..97c4c0e 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -21,12 +21,21 @@ #include <soc/intel/common/vbt.h> enum { - SKU_0_ASTRONAUT = 0, - SKU_1_ASTRONAUT = 1, + SKU_0_ASTRONAUT = 0, + SKU_1_ASTRONAUT = 1, SKU_2_SANTA = 2, SKU_3_SANTA = 3, - SKU_61_ASTRONAUT = 61, - SKU_62_ASTRONAUT = 62, + SKU_4_LAVA = 4, + SKU_5_LAVA = 5, + SKU_6_BLUE = 6, + SKU_7_BLUE = 7, + SKU_8_BRUCE = 8, + SKU_9_LAVA = 9, + SKU_10_LAVA = 10, + SKU_11_BRUCE = 11, + SKU_12_BLUE = 12, + SKU_61_ASTRONAUT = 61, + SKU_62_ASTRONAUT = 62, SKU_160_NASHER = 160, SKU_161_NASHER = 161, SKU_162_NASHER = 162, @@ -66,18 +75,63 @@ switch (sku_id) { case SKU_0_ASTRONAUT: case SKU_1_ASTRONAUT: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 2; - break; - case SKU_2_SANTA: - case SKU_3_SANTA: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 2; - break; case SKU_61_ASTRONAUT: case SKU_62_ASTRONAUT: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 5; + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; + case SKU_2_SANTA: + case SKU_3_SANTA: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; + case SKU_4_LAVA: + case SKU_5_LAVA: + case SKU_9_LAVA: + case SKU_10_LAVA: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; + case SKU_6_BLUE: + case SKU_7_BLUE: + case SKU_12_BLUE: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; + break; + case SKU_8_BRUCE: + case SKU_11_BRUCE: + cfg->usb2eye[1].Usb20PerPortPeTxiSet = 4; + cfg->usb2eye[1].Usb20PerPortTxiSet = 4; + cfg->usb2eye[1].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[1].Usb20PerPortTxPeHalf = 0; + cfg->usb2eye[4].Usb20PerPortPeTxiSet = 7; + cfg->usb2eye[4].Usb20PerPortTxiSet = 7; + cfg->usb2eye[4].Usb20IUsbTxEmphasisEn = 1; + cfg->usb2eye[4].Usb20PerPortTxPeHalf = 0; break; default: break; -- To view, visit https://review.coreboot.org/23880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I045c14ef87a5920666dc06c2b53f0fed0b702d0e Gerrit-Change-Number: 23880 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com>

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coreboot-gerrit February 2018