coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24905 ) Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... Patch Set 2: Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22487/ : SUCCESS -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:47:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24905 to look at the new patch set (#3). Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... drivers/tpm: Add TPM ramstage driver for devices without vboot. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/intel/fsp1_1/romstage.c A src/drivers/tpm/Kconfig A src/drivers/tpm/Makefile.inc A src/drivers/tpm/tpm.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/security/tpm/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 19 files changed, 48 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/24905/3 -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support for GSPI
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24906 ) Change subject: [WIP]soc/intel/apollolake: Add support for GSPI ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68008/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22485/ : SUCCESS -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:44:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Interface FSP 2.0 mrc caching ...................................................................... Patch Set 2: Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/22486/ : SUCCESS -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:44:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24904 to look at the new patch set (#3). Change subject: security/vboot: Interface FSP 2.0 mrc caching ...................................................................... security/vboot: Interface FSP 2.0 mrc caching * Add weak interface for multiple mrc hash and verify implementations. * Move vboot/tpm specific implementation to vboot. Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- A src/drivers/intel/fsp2_0/include/fsp/memory_init.h M src/drivers/intel/fsp2_0/memory_init.c A src/security/vboot/mrc_cache_hash_tpm.c 3 files changed, 148 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/24904/3 -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24903 to look at the new patch set (#7). Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... security/tpm: Unify the coreboot TPM software stack * Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/Makefile.inc M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc D src/drivers/pc80/tpm/romstage.c M src/drivers/spi/tpm/Kconfig M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/chell/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/lars/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/link/romstage.c M src/mainboard/google/oak/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/parrot/romstage.c M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/stout/romstage.c M src/mainboard/google/zoombini/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tis.h A src/security/tpm/tspi.h A src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h A src/security/tpm/tss/common/tss_common.h M src/security/tpm/tss/tcg-1.2/tss.c A src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h M src/security/tpm/tss/tcg-2.0/tss_structures.h A src/security/tpm/tss/vendor/cr50/Kconfig A src/security/tpm/tss/vendor/cr50/tss.c A src/security/tpm/tss/vendor/cr50/tss_structures.h D src/security/tpm/tss_constants.h D src/security/tpm/tss_error_messages.h A src/security/tpm/tss_errors.h M src/security/vboot/Kconfig R src/security/vboot/antirollback.h M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc 93 files changed, 1,059 insertions(+), 1,352 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/24903/7 -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support for GSPI
by Ravishankar Sarawadi (Code Review) 27 Feb '18

27 Feb '18

Hello Srinidhi N Kaushik, Shamile Khan, Shaunak Saha, build bot (Jenkins), Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/24906 to look at the new patch set (#2). Change subject: [WIP]soc/intel/apollolake: Add support for GSPI ...................................................................... [WIP]soc/intel/apollolake: Add support for GSPI BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/chip.h A src/soc/intel/apollolake/gspi.c M src/soc/intel/apollolake/include/soc/iomap.h 5 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/24906/2 -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support for GSPI
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24906 ) Change subject: [WIP]soc/intel/apollolake: Add support for GSPI ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68007/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22484/ : SUCCESS -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:39:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support for GSPI
by Ravishankar Sarawadi (Code Review) 27 Feb '18

27 Feb '18

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/24906 Change subject: [WIP]soc/intel/apollolake: Add support for GSPI ...................................................................... [WIP]soc/intel/apollolake: Add support for GSPI BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/chip.h A src/soc/intel/apollolake/gspi.c M src/soc/intel/apollolake/include/soc/iomap.h 5 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/24906/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 9729773..585b8dd 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -9,6 +9,7 @@ select SOC_INTEL_APOLLOLAKE select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_SGX + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 help Intel GLK support @@ -374,4 +375,8 @@ help Use eSPI bus instead of LPC +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 3 + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 68f2947..ab4da93 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,6 +11,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += heci.c +bootblock-$(CONFIG_SOC_INTEL_GLK) += gspi.c bootblock-y += i2c.c bootblock-y += lpc.c bootblock-y += mmap_boot.c @@ -21,6 +22,7 @@ romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c romstage-y += heci.c romstage-y += i2c.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c @@ -48,6 +50,7 @@ ramstage-y += cse.c ramstage-y += elog.c ramstage-y += graphics.c +ramstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c ramstage-y += heci.c ramstage-y += i2c.c ramstage-y += lpc.c @@ -73,6 +76,7 @@ verstage-y += car.c verstage-y += i2c.c +verstage-$(CONFIG_SOC_INTEL_GLK) += gspi.c verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 8573cf4..681d244 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,6 +20,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include <commonlib/helpers.h> +#include <intelblocks/gspi.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <intelblocks/lpc_lib.h> @@ -38,6 +39,9 @@ }; struct soc_intel_apollolake_config { + /* GSPI */ + struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/gspi.c b/src/soc/intel/apollolake/gspi.c new file mode 100644 index 0000000..ca48aac --- /dev/null +++ b/src/soc/intel/apollolake/gspi.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <device/device.h> +#include <intelblocks/gspi.h> +#include <intelblocks/spi.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include "chip.h" + +const struct gspi_cfg *gspi_get_soc_cfg(void) +{ + DEVTREE_CONST struct soc_intel_apollolake_config *config; + int devfn = SA_DEVFN_ROOT; + DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + config = dev->chip_info; + + return &config->gspi[0]; +} + +uintptr_t gspi_get_soc_early_base(void) +{ + return EARLY_GSPI_BASE_ADDRESS; +} + +/* + * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust + * the bus # accordingly when referring to SPI / GSPI bus numbers. + */ +#define GSPI_TO_SPI_BUS(x) ((x) + 1) +#define SPI_TO_GSPI_BUS(x) ((x) - 1) + +int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus) +{ + if (spi_bus == 0) + return -1; + + *gspi_bus = SPI_TO_GSPI_BUS(spi_bus); + if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + return 0; +} + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus)); +} diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d4cd095..7e6a795 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -48,6 +48,7 @@ /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 /* Temporary BAR for early I2C bus access */ #define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x))) -- To view, visit https://review.coreboot.org/24906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Gerrit-Change-Number: 24906 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24905 ) Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68006/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22483/ : SUCCESS -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:35:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018