coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

1 participants
1573 discussions

Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/24905 ) Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/24905/3/src/drivers/tpm/Kconfig File src/drivers/tpm/Kconfig: https://review.coreboot.org/#/c/24905/3/src/drivers/tpm/Kconfig@4 PS3, Line 4: depends on !VBOOT > Could you please add some documentation here explaining what the purpose of this config is? Ack https://review.coreboot.org/#/c/24905/3/src/drivers/tpm/tpm.c File src/drivers/tpm/tpm.c: https://review.coreboot.org/#/c/24905/3/src/drivers/tpm/tpm.c@21 PS3, Line 21: #include <security/tpm/tspi.h> > Doesn't seem all these #includes are necessary. Ack -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 22:43:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Interface FSP 2.0 mrc caching ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/24904/3/src/drivers/intel/fsp2_0/include/fs… File src/drivers/intel/fsp2_0/include/fsp/memory_init.h: https://review.coreboot.org/#/c/24904/3/src/drivers/intel/fsp2_0/include/fs… PS3, Line 18: > #include the header which defines the types you use. Ack https://review.coreboot.org/#/c/24904/3/src/security/vboot/mrc_cache_hash_t… File src/security/vboot/mrc_cache_hash_tpm.c: https://review.coreboot.org/#/c/24904/3/src/security/vboot/mrc_cache_hash_t… PS3, Line 4: * Copyright (C) 2018 Facebook Inc > Pretty usre it's not just facebook Ack -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 22:42:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/tpm: Implement hashing function in TSS
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24908 ) Change subject: security/tpm: Implement hashing function in TSS ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68014/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22490/ : SUCCESS -- To view, visit https://review.coreboot.org/24908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c570a6725ff2f26c9d480303eff273ae9d5ac3b Gerrit-Change-Number: 24908 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 22:32:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/tpm: Implement hashing function in TSS
by Philipp Deppenwiese (Code Review) 27 Feb '18

27 Feb '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24908 Change subject: security/tpm: Implement hashing function in TSS ...................................................................... security/tpm: Implement hashing function in TSS * Implement hash_start, hash_update and hash_complete functionality of the TPM into the TSS. * TPM 1.2 and 2.0 support. Change-Id: I6c570a6725ff2f26c9d480303eff273ae9d5ac3b Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss_errors.h 6 files changed, 121 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/24908/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 151d450..1b928ab 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -159,6 +159,22 @@ uint8_t *out_digest); /** + * Hash start function, returns size of data which can hashed at once. + */ +uint32_t tlcl_hash_start(uint32_t *data_length); + +/** + * Hash update function, measures a message into the hash. + */ +uint32_t tlcl_hash_update(const void *message, uint32_t message_length); + +/** + * Hash complete function, hashes the lastest chunk and returns the digest. + */ +uint32_t tlcl_hash_complete(const void *message, uint32_t message_length, + uint8_t *digest, uint32_t *digest_length); + +/** * Get the entire set of permanent flags. */ uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags); diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index b6a61c1..0d317e0 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -352,3 +352,68 @@ kPcrDigestLength); return result; } + +uint32_t tlcl_hash_start(uint32_t *data_length) +{ + struct s_tpm_sha1_start_cmd cmd = tpm_sha1_start_cmd; + uint8_t response[kTpmResponseHeaderLength + sizeof(uint32_t)]; + uint32_t result; + + result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + + if (data_length) { + from_tpm_uint32(response + kTpmResponseHeaderLength, + data_length); + if (*data_length >= TPM_MAX_COMMAND_SIZE) + *data_length = TPM_MAX_COMMAND_SIZE; + } + + return result; +} + +uint32_t tlcl_hash_update(const void *message, uint32_t message_length) +{ + struct s_tpm_sha1_update_cmd cmd = tpm_sha1_update_cmd; + uint32_t total_length; + uint8_t response[TPM_MAX_COMMAND_SIZE]; + + total_length = + kTpmRequestHeaderLength + sizeof(uint32_t) + message_length; + assert(total_length <= TPM_MAX_COMMAND_SIZE); + set_tpm_command_size(cmd.buffer, total_length); + + to_tpm_uint32(cmd.buffer + tpm_sha1_update_cmd.length, message_length); + memcpy(cmd.buffer + tpm_sha1_update_cmd.data, message, message_length); + + return tlcl_send_receive(cmd.buffer, response, sizeof(response)); +} + +uint32_t tlcl_hash_complete(const void *message, uint32_t message_length, + uint8_t *digest, uint32_t *digest_length) +{ + struct s_tpm_sha1_complete_cmd cmd = tpm_sha1_complete_cmd; + uint32_t total_length; + uint32_t result; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + total_length = + kTpmRequestHeaderLength + sizeof(uint32_t) + message_length; + assert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); + set_tpm_command_size(cmd.buffer, total_length); + + to_tpm_uint32(cmd.buffer + tpm_sha1_complete_cmd.length, + message_length); + memcpy(cmd.buffer + tpm_sha1_complete_cmd.data, message, + message_length); + + result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); + if (result == TPM_SUCCESS) { + memcpy(digest, response + kTpmResponseHeaderLength, + kPcrDigestLength); + *digest_length = TPM_PCR_DIGEST; + } + + return result; +} diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h index f245664..e9e77b2 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_commands.h +++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h @@ -173,5 +173,26 @@ 12, 70, 77, }; +const struct s_tpm_sha1_start_cmd{ + uint8_t buffer[10]; +} tpm_sha1_start_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0xa0, }, +}; + +const struct s_tpm_sha1_update_cmd{ + uint8_t buffer[64]; + uint16_t length; + uint16_t data; +} tpm_sha1_update_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0xa1, }, + 10, 14, }; + +const struct s_tpm_sha1_complete_cmd{ + uint8_t buffer[64]; + uint16_t length; + uint16_t data; +} tpm_sha1_complete_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0xa2, }, + 10, 14, }; + const int kWriteInfoLength = 12; const int kNvDataPublicPermissionsOffset = 60; diff --git a/src/security/tpm/tss/tcg-1.2/tss_structures.h b/src/security/tpm/tss/tcg-1.2/tss_structures.h index 9429b79..c9ac8cf 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_structures.h +++ b/src/security/tpm/tss/tcg-1.2/tss_structures.h @@ -11,10 +11,13 @@ #include <stdint.h> #include "../common/tss_common.h" -#define TPM_MAX_COMMAND_SIZE 4096 +#define TPM_MAX_COMMAND_SIZE 1400 #define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ #define TPM_PUBEK_SIZE 256 +#define TPM_HASH_MIN_COUNT 64 +#define TPM_HASH_MAX_COUNT 1024 + #define TPM_NV_INDEX0 ((uint32_t)0x00000000) #define TPM_NV_INDEX_LOCK ((uint32_t)0xffffffff) #define TPM_NV_PER_GLOBALLOCK (((uint32_t)1)<<15) diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index b64593a..5731be1 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -321,3 +321,17 @@ return TPM_SUCCESS; } + +uint32_t tlcl_hash_start(uint32_t *data_length) +{ + return NOT_IMPLEMENTED; +} +uint32_t tlcl_hash_update(const void *message, uint32_t message_length) +{ + return NOT_IMPLEMENTED; +} +uint32_t tlcl_hash_complete(const void *message, uint32_t message_length, + uint8_t *digest, uint32_t *digest_length) +{ + return NOT_IMPLEMENTED; +} diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index e2f1486..e958ef2 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -14,6 +14,7 @@ #define TPM_E_BASE 0x0 #define TPM_E_NON_FATAL 0x800 +#define NOT_IMPLEMENTED 0x100 #define TPM_E_AREA_LOCKED ((uint32_t)0x0000003c) #define TPM_E_BADINDEX ((uint32_t)0x00000002) -- To view, visit https://review.coreboot.org/24908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6c570a6725ff2f26c9d480303eff273ae9d5ac3b Gerrit-Change-Number: 24908 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: [WIP]mb/octopus: Add gpio configs for communities
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23799 ) Change subject: [WIP]mb/octopus: Add gpio configs for communities ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68012/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22488/ : SUCCESS -- To view, visit https://review.coreboot.org/23799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Gerrit-Change-Number: 23799 Gerrit-PatchSet: 7 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 22:25:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP]mb/google/octopus: Enable TPM on GSPI
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24907 ) Change subject: [WIP]mb/google/octopus: Enable TPM on GSPI ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68013/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22489/ : SUCCESS -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 22:07:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: [WIP]mb/google/octopus: Enable TPM on GSPI
by Ravishankar Sarawadi (Code Review) 27 Feb '18

27 Feb '18

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/24907 Change subject: [WIP]mb/google/octopus: Enable TPM on GSPI ...................................................................... [WIP]mb/google/octopus: Enable TPM on GSPI BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/gpio.c 3 files changed, 41 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/24907/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 0f30316..f1c8d8f 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -63,4 +63,20 @@ config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." +config DRIVER_TPM_SPI_BUS + depends on OCTOPUS_USE_SPI_TPM + default 0x1 + +# Select this option to enable use of cr50 SPI TPM on octopus. +config OCTOPUS_USE_SPI_TPM + bool + default y + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM + select TPM2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 63 # GPE0_DW1_31 (GPIO_63) + endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 6248a88..5f34fd9 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -3,6 +3,13 @@ device lapic 0 on end end + # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM + # communication before memory is up. + register "gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF @@ -69,7 +76,14 @@ device pci 18.1 off end # - UART 1 device pci 18.2 on end # - UART 2 device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 + device pci 19.0 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63)" + device spi 0 on end + end + end # - GSPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 on end # - SPI 2 device pci 1a.0 on end # - PWM diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 5bd2556..6c78782 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -266,6 +266,16 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { +#if IS_ENABLED(CONFIG_OCTOPUS_USE_SPI_TPM) +/* GSPI0_CLK */ PAD_CFG_NF(GPIO_79, NONE, DEEP, + NF1), /* H1_SLAVE_SPI_CLK_R */ +/* GSPI0_CS# */ PAD_CFG_NF(GPIO_80, NONE, DEEP, + NF1), /* H1_SLAVE_SPI_CS_L_R */ +/* GSPI0_MISO */ PAD_CFG_NF(GPIO_81, NONE, DEEP, + NF1), /* H1_SLAVE_SPI_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPIO_82, NONE, DEEP, + NF1), /* H1_SLAVE_SPI_MOSI_R */ +#endif }; const struct pad_config *__attribute__((weak)) -- To view, visit https://review.coreboot.org/24907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Gerrit-Change-Number: 24907 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

1 0

Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24905 ) Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68011/ : SUCCESS -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:53:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68009/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:49:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Interface FSP 2.0 mrc caching ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68010/ : SUCCESS -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:49:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
158
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2018