February 2018 - coreboot-gerrit

Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by Philipp Deppenwiese (Code Review) Feb. 27, 2018

Feb. 27, 2018

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24905 Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... drivers/tpm: Add TPM ramstage driver for devices without vboot. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/intel/fsp1_1/romstage.c A src/drivers/tpm/Kconfig A src/drivers/tpm/Makefile.inc A src/drivers/tpm/tpm.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/security/tpm/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 19 files changed, 48 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/24905/1 diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1c293d4..2cfc19c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -42,7 +42,6 @@ #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" #include "southbridge/intel/lynxpoint/me.h" -#include <security/tpm/tspi.h> static inline void reset_system(void) { @@ -245,8 +244,6 @@ romstage_handoff_init(wake_from_s3); post_code(0x3f); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(wake_from_s3); } asmlinkage void romstage_after_car(void) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index f542038..8515219 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -36,7 +36,6 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <security/tpm/tspi.h> #include <vendorcode/google/chromeos/chromeos.h> asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) @@ -166,16 +165,6 @@ if (romstage_handoff_init( params->power_state->prev_sleep_state == ACPI_S3) < 0) hard_reset(); - - /* - * Initialize the TPM, unless the TPM was already initialized - * in verstage and used to verify romstage. - */ - if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) && - !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && - !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) - tpm_setup(params->power_state->prev_sleep_state == - ACPI_S3); } void after_cache_as_ram_stage(void) diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig new file mode 100644 index 0000000..da8434b --- /dev/null +++ b/src/drivers/tpm/Kconfig @@ -0,0 +1,4 @@ +config TPM_INIT + bool + default y if TPM1 || TPM2 + depends on !VBOOT diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc new file mode 100644 index 0000000..4e80600 --- /dev/null +++ b/src/drivers/tpm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_TPM_INIT) += tpm.c diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c new file mode 100644 index 0000000..3799f2a --- /dev/null +++ b/src/drivers/tpm/tpm.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <stddef.h> +#include <option.h> +#include <bootstate.h> +#include <device/device.h> +#include <security/tpm/tspi.h> + +#if IS_ENABLED(CONFIG_ARCH_X86) +#include <arch/acpi.h> +#endif + +static void init_tpm_dev(void *unused) +{ +#if IS_ENABLED(CONFIG_ARCH_X86) + int s3resume = acpi_is_wakeup_s3(); + tpm_setup(s3resume); +#else + tpm_setup(false); +#endif +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_tpm_dev, NULL); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 8bcb062..aecf3b2 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -46,7 +46,6 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> -#include <security/tpm/tspi.h> #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" @@ -626,9 +625,6 @@ pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707); pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); } /** diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 9cf2cc8..bf05be9 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -35,7 +35,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tspi.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 9e68493..f44da4e 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -35,7 +35,6 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> -#include <security/tpm/tspi.h> #include "ec/compal/ene932/ec.h" void pch_enable_lpc(void) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 387ed76..ffebe53 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -35,7 +35,6 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <bootmode.h> -#include <security/tpm/tspi.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9ecfeec..5efe62d 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -35,7 +35,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tspi.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 951b40b..986226e7 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -35,7 +35,6 @@ #include <timestamp.h> #include <arch/acpi.h> #include <cbmem.h> -#include <security/tpm/tspi.h> #include "dock.h" #include "arch/early_variables.h" @@ -285,7 +284,4 @@ acpi_prepare_for_resume(); else quick_ram_check(); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 093cad6..af48e30 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <Fch/Fch.h> -#include <security/tpm/tspi.h> #include "gpio_ftns.h" @@ -103,9 +102,6 @@ post_code(0x41); AGESAWRAPPER(amdinitenv); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(false); - outb(0xEA, 0xCD6); outb(0x1, 0xcd7); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index c066ca4..d2231aa 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -28,7 +28,6 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 2572d77..2cc7e50 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -37,7 +37,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tspi.h> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index c334a51..eefbfa2 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> -#include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/chip.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> @@ -116,8 +115,5 @@ northbridge_romstage_finalize(s3resume); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); - post_code(0x3f); } diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index 74cd978..fb8edf28 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -3,16 +3,16 @@ ifeq ($(CONFIG_TPM1),y) ramstage-y += tss/tcg-1.2/tss.c -romstage-y += tss/tcg-1.2/tss.c +romstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c ## TSPI ramstage-y += tspi/tspi.c -romstage-y += tspi/tspi.c +romstage-$(CONFIG_VBOOT) += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c postcar-$(CONFIG_VBOOT) += tspi/tspi.c @@ -23,8 +23,8 @@ ramstage-y += tss/tcg-2.0/tss_marshaling.c ramstage-y += tss/tcg-2.0/tss.c -romstage-y += tss/tcg-2.0/tss_marshaling.c -romstage-y += tss/tcg-2.0/tss.c +romstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c +romstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c @@ -35,8 +35,8 @@ ## TSPI ramstage-y += tspi/tspi.c -romstage-y += tspi/tspi.c +romstage-$(CONFIG_VBOOT) += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c postcar-$(CONFIG_VBOOT) += tspi/tspi.c @@ -45,8 +45,8 @@ ifeq ($(CONFIG_TPM_CR50),y) ramstage-y += tss/vendor/cr50/tss.c -romstage-y += tss/vendor/cr50/tss.c +romstage-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c verstage-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c postcar-$(CONFIG_VBOOT) += tss/vendor/cr50/tss.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index e911724..765fc09 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -30,7 +30,6 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <security/tpm/tspi.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -228,9 +227,6 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(prev_sleep_state == ACPI_S3); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 2fbe406..f485dfd 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -43,7 +43,6 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> -#include <security/tpm/tspi.h> void program_base_addresses(void) { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f66824f..8762f9f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -25,7 +25,6 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> -#include <security/tpm/tspi.h> #include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> @@ -109,9 +108,6 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(params->power_state->prev_sleep_state == ACPI_S3); } asmlinkage void romstage_after_car(void) -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching
by build bot (Jenkins) (Code Review) Feb. 27, 2018

Feb. 27, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Interface FSP 2.0 mrc caching ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68005/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22482/ : SUCCESS -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:24:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching
by Philipp Deppenwiese (Code Review) Feb. 27, 2018

Feb. 27, 2018

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24904 Change subject: security/vboot: Interface FSP 2.0 mrc caching ...................................................................... security/vboot: Interface FSP 2.0 mrc caching Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- A src/drivers/intel/fsp2_0/include/fsp/memory_init.h M src/drivers/intel/fsp2_0/memory_init.c A src/security/vboot/mrc_cache_hash_tpm.c 3 files changed, 148 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/24904/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h new file mode 100644 index 0000000..2f21019 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FSP2_0_MEMORY_INIT_H_ +#define _FSP2_0_MEMORY_INIT_H_ + +/* + * Updates mrc cache hash if it differs. + */ +void mrc_cache_update_hash(const uint8_t *data, size_t size); + +/* + * Verifies mrc cache hash which is stored somewhere. + * return 1 verification was successful and 0 for error. + */ +int mrc_cache_verify_hash(const uint8_t *data, size_t size); + +#endif /* _FSP2_0_MEMORY_INIT_H_ */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index aa5909f..3dafa00 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -31,62 +31,19 @@ #include <string.h> #include <symbols.h> #include <timestamp.h> -#include <security/tpm/tspi.h> #include <security/vboot/vboot_common.h> #include <vb2_api.h> +#include <fsp/memory_init.h> -static void mrc_cache_update_tpm_hash(const uint8_t *data, size_t size) +__attribute__((weak)) void mrc_cache_update_hash(const uint8_t *data, + size_t size) { - uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; - static const uint8_t dead_hash[VB2_SHA256_DIGEST_SIZE] = { - 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ - 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ - 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ - 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ - 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ - 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ - 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ - 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ - }; - const uint8_t *hash_ptr = data_hash; +} - /* We do not store normal mode data hash in TPM. */ - if (!vboot_recovery_mode_enabled()) - return; - - /* Bail out early if no mrc hash space is supported in TPM. */ - if (!IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH)) - return; - - /* Initialize TPM driver. */ - if (tlcl_lib_init() != VB2_SUCCESS) { - printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); - return; - } - - /* Calculate hash of data generated by MRC. */ - if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, - sizeof(data_hash))) { - printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data. " - "Not updating TPM hash space.\n"); - /* - * Since data is being updated in recovery cache, the hash - * currently stored in TPM recovery hash space is no longer - * valid. If we are not able to calculate hash of the data being - * updated, reset all the bits in TPM recovery hash space to - * pre-defined hash pattern. - */ - hash_ptr = dead_hash; - } - - /* Write hash of data to TPM space. */ - if (antirollback_write_space_rec_hash(hash_ptr, VB2_SHA256_DIGEST_SIZE) - != TPM_SUCCESS) { - printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n"); - return; - } - - printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n"); +__attribute__((weak)) int mrc_cache_verify_hash(const uint8_t *data, + size_t size) +{ + return 1; } static void save_memory_training_data(bool s3wake, uint32_t fsp_version) @@ -113,7 +70,7 @@ mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); - mrc_cache_update_tpm_hash(mrc_data, mrc_data_size); + mrc_cache_update_hash(mrc_data, mrc_data_size); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -148,48 +105,6 @@ romstage_handoff_init(s3wake); } -static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size) -{ - uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; - uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; - - /* We do not store normal mode data hash in TPM. */ - if (!vboot_recovery_mode_enabled()) - return 1; - - if (!IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH)) - return 1; - - /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ - if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, - sizeof(data_hash))) { - printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); - return 0; - } - - /* Initialize TPM driver. */ - if (tlcl_lib_init() != VB2_SUCCESS) { - printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); - return 0; - } - - /* Read hash of MRC data saved in TPM. */ - if (antirollback_read_space_rec_hash(tpm_hash, sizeof(tpm_hash)) - != TPM_SUCCESS) { - printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n"); - return 0; - } - - if (memcmp(tpm_hash, data_hash, sizeof(tpm_hash))) { - printk(BIOS_ERR, "MRC: Hash comparison failed.\n"); - return 0; - } - - printk(BIOS_INFO, "MRC: Hash comparison successful. " - "Using data from RECOVERY_MRC_CACHE\n"); - return 1; -} - static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) { struct region_device rdev; @@ -222,7 +137,7 @@ if (data == NULL) return; - if (!mrc_cache_verify_tpm_hash(data, region_device_sz(&rdev))) + if (!mrc_cache_verify_hash(data, region_device_sz(&rdev))) return; /* MRC cache found */ diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c new file mode 100644 index 0000000..986aa63 --- /dev/null +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <security/vboot/antirollback.h> +#include <program_loading.h> +#include <security/vboot/vboot_common.h> +#include <vb2_api.h> +#include <security/tpm/tss.h> +#include <fsp/memory_init.h> +#include <console/console.h> +#include <string.h> + +void mrc_cache_update_hash(const uint8_t *data, size_t size) +{ + uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; + static const uint8_t dead_hash[VB2_SHA256_DIGEST_SIZE] = { + 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ + 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ + 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ + 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ + 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ + 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ + 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ + 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ + }; + const uint8_t *hash_ptr = data_hash; + + /* We do not store normal mode data hash in TPM. */ + if (!vboot_recovery_mode_enabled()) + return; + + /* Initialize TPM driver. */ + if (tlcl_lib_init() != VB2_SUCCESS) { + printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); + return; + } + + /* Calculate hash of data generated by MRC. */ + if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, + sizeof(data_hash))) { + printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data. " + "Not updating TPM hash space.\n"); + /* + * Since data is being updated in recovery cache, the hash + * currently stored in TPM recovery hash space is no longer + * valid. If we are not able to calculate hash of the data being + * updated, reset all the bits in TPM recovery hash space to + * pre-defined hash pattern. + */ + hash_ptr = dead_hash; + } + + /* Write hash of data to TPM space. */ + if (antirollback_write_space_rec_hash(hash_ptr, VB2_SHA256_DIGEST_SIZE) + != TPM_SUCCESS) { + printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n"); + return; + } + + printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n"); +} + +int mrc_cache_verify_hash(const uint8_t *data, size_t size) +{ + uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; + uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; + + /* We do not store normal mode data hash in TPM. */ + if (!vboot_recovery_mode_enabled()) + return 1; + + /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ + if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, + sizeof(data_hash))) { + printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); + return 0; + } + + /* Initialize TPM driver. */ + if (tlcl_lib_init() != VB2_SUCCESS) { + printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); + return 0; + } + + /* Read hash of MRC data saved in TPM. */ + if (antirollback_read_space_rec_hash(tpm_hash, sizeof(tpm_hash)) + != TPM_SUCCESS) { + printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n"); + return 0; + } + + if (memcmp(tpm_hash, data_hash, sizeof(tpm_hash))) { + printk(BIOS_ERR, "MRC: Hash comparison failed.\n"); + return 0; + } + + printk(BIOS_INFO, "MRC: Hash comparison successful. " + "Using data from RECOVERY_MRC_CACHE\n"); + return 1; +} -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) Feb. 27, 2018

Feb. 27, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68004/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22481/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 21:12:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by Philipp Deppenwiese (Code Review) Feb. 27, 2018

Feb. 27, 2018

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24903 to look at the new patch set (#6). Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... security/tpm: Unify the coreboot TPM software stack Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/Makefile.inc M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc D src/drivers/pc80/tpm/romstage.c M src/drivers/spi/tpm/Kconfig M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/chell/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/lars/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/link/romstage.c M src/mainboard/google/oak/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/parrot/romstage.c M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/stout/romstage.c M src/mainboard/google/zoombini/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tis.h A src/security/tpm/tspi.h A src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h A src/security/tpm/tss/common/tss_common.h M src/security/tpm/tss/tcg-1.2/tss.c A src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h M src/security/tpm/tss/tcg-2.0/tss_structures.h A src/security/tpm/tss/vendor/cr50/Kconfig A src/security/tpm/tss/vendor/cr50/tss.c A src/security/tpm/tss/vendor/cr50/tss_structures.h D src/security/tpm/tss_constants.h D src/security/tpm/tss_error_messages.h A src/security/tpm/tss_errors.h M src/security/vboot/Kconfig R src/security/vboot/antirollback.h M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc 93 files changed, 1,059 insertions(+), 1,352 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/24903/6 -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) Feb. 27, 2018

Feb. 27, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68003/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22480/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 20:03:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by Philipp Deppenwiese (Code Review) Feb. 27, 2018

Feb. 27, 2018

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24903 to look at the new patch set (#5). Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... security/tpm: Unify the coreboot TPM software stack Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/Makefile.inc M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc D src/drivers/pc80/tpm/romstage.c M src/drivers/spi/tpm/Kconfig M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/chell/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/lars/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/link/romstage.c M src/mainboard/google/oak/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/parrot/romstage.c M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/stout/romstage.c M src/mainboard/google/zoombini/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tis.h A src/security/tpm/tspi.h A src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h A src/security/tpm/tss/common/tss_common.h M src/security/tpm/tss/tcg-1.2/tss.c A src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h M src/security/tpm/tss/tcg-2.0/tss_structures.h A src/security/tpm/tss/vendor/cr50/Kconfig A src/security/tpm/tss/vendor/cr50/tss.c A src/security/tpm/tss/vendor/cr50/tss_structures.h D src/security/tpm/tss_constants.h D src/security/tpm/tss_error_messages.h A src/security/tpm/tss_errors.h M src/security/vboot/Kconfig R src/security/vboot/antirollback.h M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc 92 files changed, 1,057 insertions(+), 1,352 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/24903/5 -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) Feb. 27, 2018

Feb. 27, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68002/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22479/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 19:52:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by Philipp Deppenwiese (Code Review) Feb. 27, 2018

Feb. 27, 2018

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24903 to look at the new patch set (#4). Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... security/tpm: Unify the coreboot TPM software stack Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/Makefile.inc M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc D src/drivers/pc80/tpm/romstage.c M src/drivers/spi/tpm/Kconfig M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/chell/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/lars/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/link/romstage.c M src/mainboard/google/oak/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/parrot/romstage.c M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/stout/romstage.c M src/mainboard/google/zoombini/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tis.h A src/security/tpm/tspi.h A src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h A src/security/tpm/tss/common/tss_common.h M src/security/tpm/tss/tcg-1.2/tss.c A src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_structures.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h M src/security/tpm/tss/tcg-2.0/tss_structures.h A src/security/tpm/tss/vendor/cr50/Kconfig A src/security/tpm/tss/vendor/cr50/tss.c A src/security/tpm/tss/vendor/cr50/tss_structures.h D src/security/tpm/tss_constants.h D src/security/tpm/tss_error_messages.h A src/security/tpm/tss_errors.h M src/security/vboot/Kconfig R src/security/vboot/antirollback.h M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc 92 files changed, 1,058 insertions(+), 1,351 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/24903/4 -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/tpm: Unify the coreboot TPM software stack
by build bot (Jenkins) (Code Review) Feb. 27, 2018

Feb. 27, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24903 ) Change subject: security/tpm: Unify the coreboot TPM software stack ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68001/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22478/ : SUCCESS -- To view, visit https://review.coreboot.org/24903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Gerrit-Change-Number: 24903 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 19:15:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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