coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

1 participants
1573 discussions

Change in coreboot[master]: mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting
by Seunghwan Kim (Code Review) 27 Feb '18

27 Feb '18

Seunghwan Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/23877 ) Change subject: mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting ...................................................................... mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting This change sets SlowSlewRateForSa setting to Fast/8. It can make nautilus board to avoid flicker issue at VT2. BUG=b:71397040 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23877/2 -- To view, visit https://review.coreboot.org/23877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Gerrit-Change-Number: 23877 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

1 0

Change in coreboot[master]: mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting
by Seunghwan Kim (Code Review) 27 Feb '18

27 Feb '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/23877 Change subject: mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting ...................................................................... mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting This change sets SlowSlewRateForSa setting to Fast/8. It can make nautilus board to avoid flicker issue at VT2. BUG=b:71397040 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23877/1 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 3c87b27..0f24685 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -77,7 +77,8 @@ register "FastPkgCRampDisableSa" = "1" register "SlowSlewRateForIa" = "3" # Fast/16 register "SlowSlewRateForGt" = "3" # Fast/16 - register "SlowSlewRateForSa" = "3" # Fast/16 + register "SlowSlewRateForSa" = "2" # Fast/8 + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/23877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Gerrit-Change-Number: 23877 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

1 0

Change in coreboot[master]: skylake: Fix unwanted disablement of ACPI UPWE
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23848 ) Change subject: skylake: Fix unwanted disablement of ACPI UPWE ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67958/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22438/ : SUCCESS -- To view, visit https://review.coreboot.org/23848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Gerrit-Change-Number: 23848 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 03:18:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: util/cbfstool: Add ARM64 Image support
by Julius Werner (Code Review) 27 Feb '18

27 Feb '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/23869 ) Change subject: util/cbfstool: Add ARM64 Image support ...................................................................... Patch Set 2: I'm a little confused why we need a trampoline and relocation code just to boot an ARM64 kernel. ARM64 kernels always want to be loaded at the start of physical memory (+0x80000). ARM64 boards in coreboot can statically position their ramstage wherever they want in memlayout. Why not just make sure that the ramstage is always far enough away from the start of physical memory to avoid the possibility of an overlap and be done with it? I mean, all relevant systems have more than enough DRAM available. This just seems to add loads of complication to the process with no clear gain. -- To view, visit https://review.coreboot.org/23869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a8183a87de4dc3a4c4f038fe5b4912ada5d75f9 Gerrit-Change-Number: 23869 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 01:59:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19820 ) Change subject: mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67957/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22437/ : SUCCESS -- To view, visit https://review.coreboot.org/19820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5 Gerrit-Change-Number: 19820 Gerrit-PatchSet: 7 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: James Hebden <james(a)hebden.net.au> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Feb 2018 01:44:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Initial support for new mainboard Cheza
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23861 ) Change subject: Initial support for new mainboard Cheza ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67956/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22436/ : SUCCESS -- To view, visit https://review.coreboot.org/23861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I65d91dbefa3094f94618e50020280c0e1e4fade9 Gerrit-Change-Number: 23861 Gerrit-PatchSet: 2 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Feb 2018 01:02:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Initial support for new mainboard Cheza
by Julius Werner (Code Review) 27 Feb '18

27 Feb '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/23875 ) Change subject: Initial support for new mainboard Cheza ...................................................................... Patch Set 1: Hi Thomas, Looks like you're trying to upload updates to your existing CL? You have to make sure that you keep the "Change-Id: ..." string in the commit message the same when uploading an update to an existing patch, so that Gerrit knows they belong together. Right now you have created three separate CLs with the same patch. Please re-upload your latest version with the Change-Id changed to the one from your initial upload (Change-Id: I65d91dbefa3094f94618e50020280c0e1e4fade9), and abandon these other ones. -- To view, visit https://review.coreboot.org/23875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51c28455987f042e6b64a572ec2787947f29bb99 Gerrit-Change-Number: 23875 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Feb 2018 00:40:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/octopus: Add LPDDR4 memory init
by build bot (Jenkins) (Code Review) 27 Feb '18

27 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23832 ) Change subject: mb/google/octopus: Add LPDDR4 memory init ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67955/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22435/ : SUCCESS -- To view, visit https://review.coreboot.org/23832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9 Gerrit-Change-Number: 23832 Gerrit-PatchSet: 5 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 23:20:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Initial support for new mainboard Cheza
by build bot (Jenkins) (Code Review) 26 Feb '18

26 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23876 ) Change subject: Initial support for new mainboard Cheza ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67954/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22434/ : SUCCESS -- To view, visit https://review.coreboot.org/23876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I91226c2bc88dd10bc2590d1689267306763bb63e Gerrit-Change-Number: 23876 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 26 Feb 2018 22:55:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Initial support for new mainboard Cheza
by T.Michael Turney (Code Review) 26 Feb '18

26 Feb '18

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/23876 to review the following change. Change subject: Initial support for new mainboard Cheza ...................................................................... Initial support for new mainboard Cheza Successful build with minimal configuration Most functions are stubbed out, w/minimal content Change-Id: I91226c2bc88dd10bc2590d1689267306763bb63e Signed-off-by: T.Michael Turney <mturney(a)codeaurora.org> --- A src/mainboard/google/cheza/Kconfig A src/mainboard/google/cheza/Kconfig.name A src/mainboard/google/cheza/Makefile.inc A src/mainboard/google/cheza/board_info.txt A src/mainboard/google/cheza/bootblock.c A src/mainboard/google/cheza/chromeos.c A src/mainboard/google/cheza/chromeos.fmd A src/mainboard/google/cheza/devicetree.cb A src/mainboard/google/cheza/mainboard.c A src/mainboard/google/cheza/memlayout.ld A src/mainboard/google/cheza/romstage.c A src/soc/qualcomm/sdm845/Kconfig A src/soc/qualcomm/sdm845/Makefile.inc A src/soc/qualcomm/sdm845/bootblock.c A src/soc/qualcomm/sdm845/cbmem.c A src/soc/qualcomm/sdm845/i2c.c A src/soc/qualcomm/sdm845/include/soc/gpio.h A src/soc/qualcomm/sdm845/include/soc/memlayout.ld A src/soc/qualcomm/sdm845/soc.c A src/soc/qualcomm/sdm845/spi.c A src/soc/qualcomm/sdm845/stage_entry.c A src/soc/qualcomm/sdm845/timer.c 22 files changed, 708 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/23876/1 diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig new file mode 100644 index 0000000..4f3e94e --- /dev/null +++ b/src/mainboard/google/cheza/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variant boards. + def_bool n + +if BOARD_GOOGLE_CHEZA_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 + select COMMON_CBFS_SPI_WRAPPER + select SOC_QUALCOMM_SDM845 + select SPI_FLASH + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select VBOOT_VBNV_FLASH + select TPM + +config MAINBOARD_DIR + string + default google/cheza + +config MAINBOARD_VENDOR + string + default "Google" + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "Cheza" if BOARD_GOOGLE_CHEZA + +config GBB_HWID + string + depends on CHROMEOS + default "CHEZA TEST 845" if BOARD_GOOGLE_CHEZA + +endif # BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name new file mode 100644 index 0000000..2697c0b --- /dev/null +++ b/src/mainboard/google/cheza/Kconfig.name @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_GOOGLE_CHEZA + bool "Cheza (Qualcomm Chromebook)" + select BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc new file mode 100644 index 0000000..de33112 --- /dev/null +++ b/src/mainboard/google/cheza/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += memlayout.ld +bootblock-y += chromeos.c +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/cheza/board_info.txt new file mode 100644 index 0000000..5498070 --- /dev/null +++ b/src/mainboard/google/cheza/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cheza Qualcomm reference board +Category: eval +ROM protocol: QSPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c new file mode 100644 index 0000000..aceb61b --- /dev/null +++ b/src/mainboard/google/cheza/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_early_init(void) +{ + +} + +void bootblock_mainboard_init(void) +{ + +} diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c new file mode 100644 index 0000000..98c1285 --- /dev/null +++ b/src/mainboard/google/cheza/chromeos.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> + +int get_write_protect_state(void); +int get_recovery_mode_switch(void); + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_write_protect_state(void) +{ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd new file mode 100644 index 0000000..d00b5c0 --- /dev/null +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +FLASH@0x0 0x200000 { + WP_RO@0x0 0x000AB100 { + RO_SECTION@0x0 0x000A9100 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x80000 + FMAP@0xA0000 0x1000 + GBB@0xA1000 0x8000 + RO_FRID@0xA9000 0x100 + } + RO_VPD@0xA9100 0x2000 + } + RW_NVRAM@0xAB100 0x2000 + RW_ELOG@0xAD100 0x2000 + RW_VPD@0xAF100 0x2000 + RW_CDT@0xB1100 0x2000 + + RW_SECTION_A@0xB3100 0x8A100 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x80000 + RW_FWID_A@0x82000 0x100 + RW_DDR_TRAINING_A@0x82100 0x4000 + RW_XBL_BUFFER_A@0x86100 0x4000 + } + RW_SHARED@0x13D200 0x1000 { + SHARED_DATA@0x0 0x1000 + } + RW_SECTION_B@0x13E200 0x8A100 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x80000 + RW_FWID_B@0x82000 0x100 + RW_DDR_TRAINING_B@0x82100 0x4000 + RW_XBL_BUFFER_B@0x86100 0x4000 + } +} diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb new file mode 100644 index 0000000..41942f1 --- /dev/null +++ b/src/mainboard/google/cheza/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/qualcomm/sdm845 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c new file mode 100644 index 0000000..6a3fad9 --- /dev/null +++ b/src/mainboard/google/cheza/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <bootblock_common.h> + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld new file mode 100644 index 0000000..1ae10a5 --- /dev/null +++ b/src/mainboard/google/cheza/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include <soc/memlayout.ld> diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c new file mode 100644 index 0000000..8f25898 --- /dev/null +++ b/src/mainboard/google/cheza/romstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/exception.h> +#include <cbmem.h> +#include <program_loading.h> + +void main(void) +{ + exception_init(); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig new file mode 100644 index 0000000..747052e --- /dev/null +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_QUALCOMM_SDM845 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + +if SOC_QUALCOMM_SDM845 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc new file mode 100644 index 0000000..1d76649 --- /dev/null +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += i2c.c + +################################################################################ +verstage-y += stage_entry.c +verstage-y += timer.c +verstage-y += spi.c +verstage-y += i2c.c + +################################################################################ +romstage-y += stage_entry.c +romstage-y += timer.c +romstage-y += spi.c +romstage-y += cbmem.c +romstage-y += i2c.c + +################################################################################ +ramstage-y += stage_entry.c +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += cbmem.c +ramstage-y += i2c.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c new file mode 100644 index 0000000..3440dd7 --- /dev/null +++ b/src/soc/qualcomm/sdm845/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <string.h> + +extern u8 _bss[], _ebss[]; + +void bootblock_soc_early_init(void) +{ + memset(_bss, 0, (_ebss-_bss)); +} + +void bootblock_soc_init(void) +{ + +} diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c new file mode 100644 index 0000000..45cda8f --- /dev/null +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return NULL; +} diff --git a/src/soc/qualcomm/sdm845/i2c.c b/src/soc/qualcomm/sdm845/i2c.c new file mode 100644 index 0000000..8ce6f54 --- /dev/null +++ b/src/soc/qualcomm/sdm845/i2c.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/i2c_simple.h> + +int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, + int seg_count) +{ + return 0; +} diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h new file mode 100644 index 0000000..9b2a0f4 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_ +#define _SOC_QUALCOMM_SDM845_GPIO_H_ + +#include <types.h> + +typedef u32 gpio_t; + +#endif // _SOC_QUALCOMM_SDM845_GPIO_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld new file mode 100644 index 0000000..a81df2c --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +#define SRAM_XBL_START(addr) SYMBOL(xbl, addr) +#define SRAM_XBL_END(addr) SYMBOL(exbl, addr) + +#define SRAM2_START(addr) SYMBOL(sram2, addr) +#define SRAM2_END(addr) SYMBOL(esram2, addr) + +#define SRAM3_START(addr) SYMBOL(sram3, addr) +#define SRAM3_END(addr) SYMBOL(esram3, addr) + +#define SRAM4_START(addr) SYMBOL(sram4, addr) +#define SRAM4_END(addr) SYMBOL(esram4, addr) + +// SYSTEM_IMEM : 0x14680000 - 0x146C0000 +// BOOT_IMEM : 0x14800000 - 0x14980000 + +SECTIONS +{ + SRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 95K) + SRAM_END(0x1469FC00) + + SRAM2_START(0x146A0000) + // This area, used by other firmware in system + SRAM2_END(0x146C0000) + + SRAM3_START(0x14800000) + // This area, contains PBL shared data & mmu non-cacheable areas + SRAM3_END(0x14816000) + + SRAM4_START(0x14816000) + BOOTBLOCK(0x14816000, 32K) + TTB(0x1481E000, 64K) + VBOOT2_WORK(0x1482E000, 16K) + STACK(0x14832000, 16K) + TIMESTAMP(0x14836000, 1K) + PRERAM_CBMEM_CONSOLE(0x14836400, 32K) + PRERAM_CBFS_CACHE(0x1483E400, 70K) + SRAM_XBL_START(0x1484FC00) + // size available is 1217KB + // qclib.elf starts at 0x148F2000, 512KB + // dcb.elf starts at 0x14972000, 8KB + // pmic.elf starts at 0x14974000, 48KB + SRAM_XBL_END(0x14980000) + SRAM4_END(0x14980000) + + DRAM_START(0x80000000) + RAMSTAGE(0x80800000, 128K) + SYMBOL(memlayout_cbmem_top, 0xA1000000) + POSTRAM_CBFS_CACHE(0xA1000000, 384K) +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c new file mode 100644 index 0000000..9f2fbc4 --- /dev/null +++ b/src/soc/qualcomm/sdm845/soc.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void soc_read_resources(device_t dev) +{ + +} + +static void soc_init(device_t dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sdm845_ops = { + CHIP_NAME("SOC Qualcomm SDM845") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c new file mode 100644 index 0000000..175b6cf --- /dev/null +++ b/src/soc/qualcomm/sdm845/spi.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + return 0; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + return 0; +} + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sdm845/stage_entry.c b/src/soc/qualcomm/sdm845/stage_entry.c new file mode 100644 index 0000000..4cfa9bd --- /dev/null +++ b/src/soc/qualcomm/sdm845/stage_entry.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <string.h> + +extern u8 _bss[], _ebss[]; +extern void main(void); +void stage_entry(void); + +void stage_entry(void) +{ + memset(_bss, 0, (_ebss-_bss)); + main(); +} diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c new file mode 100644 index 0000000..b1df161 --- /dev/null +++ b/src/soc/qualcomm/sdm845/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <delay.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + +} + +void init_timer(void) +{ + +} -- To view, visit https://review.coreboot.org/23876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I91226c2bc88dd10bc2590d1689267306763bb63e Gerrit-Change-Number: 23876 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2018