February 2018 - coreboot-gerrit

Change in coreboot[master]: Initial support for new mainboard Cheza
by build bot (Jenkins) (Code Review) Feb. 26, 2018

Feb. 26, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23875 ) Change subject: Initial support for new mainboard Cheza ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67953/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22433/ : SUCCESS -- To view, visit https://review.coreboot.org/23875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51c28455987f042e6b64a572ec2787947f29bb99 Gerrit-Change-Number: 23875 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 26 Feb 2018 22:20:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Initial support for new mainboard Cheza
by T.Michael Turney (Code Review) Feb. 26, 2018

Feb. 26, 2018

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/23875 to review the following change. Change subject: Initial support for new mainboard Cheza ...................................................................... Initial support for new mainboard Cheza Successful build with minimal configuration Most functions are stubbed out, w/minimal content Change-Id: I51c28455987f042e6b64a572ec2787947f29bb99 Signed-off-by: T.Michael Turney <mturney(a)codeaurora.org> --- A src/mainboard/google/cheza/Kconfig A src/mainboard/google/cheza/Kconfig.name A src/mainboard/google/cheza/Makefile.inc A src/mainboard/google/cheza/board_info.txt A src/mainboard/google/cheza/bootblock.c A src/mainboard/google/cheza/chromeos.c A src/mainboard/google/cheza/chromeos.fmd A src/mainboard/google/cheza/devicetree.cb A src/mainboard/google/cheza/mainboard.c A src/mainboard/google/cheza/memlayout.ld A src/mainboard/google/cheza/romstage.c A src/soc/qualcomm/sdm845/Kconfig A src/soc/qualcomm/sdm845/Makefile.inc A src/soc/qualcomm/sdm845/bootblock.c A src/soc/qualcomm/sdm845/cbmem.c A src/soc/qualcomm/sdm845/i2c.c A src/soc/qualcomm/sdm845/include/soc/gpio.h A src/soc/qualcomm/sdm845/include/soc/memlayout.ld A src/soc/qualcomm/sdm845/soc.c A src/soc/qualcomm/sdm845/spi.c A src/soc/qualcomm/sdm845/stage_entry.c A src/soc/qualcomm/sdm845/timer.c 22 files changed, 709 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/23875/1 diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig new file mode 100644 index 0000000..4f3e94e --- /dev/null +++ b/src/mainboard/google/cheza/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variant boards. + def_bool n + +if BOARD_GOOGLE_CHEZA_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 + select COMMON_CBFS_SPI_WRAPPER + select SOC_QUALCOMM_SDM845 + select SPI_FLASH + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select VBOOT_VBNV_FLASH + select TPM + +config MAINBOARD_DIR + string + default google/cheza + +config MAINBOARD_VENDOR + string + default "Google" + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "Cheza" if BOARD_GOOGLE_CHEZA + +config GBB_HWID + string + depends on CHROMEOS + default "CHEZA TEST 845" if BOARD_GOOGLE_CHEZA + +endif # BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name new file mode 100644 index 0000000..2697c0b --- /dev/null +++ b/src/mainboard/google/cheza/Kconfig.name @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_GOOGLE_CHEZA + bool "Cheza (Qualcomm Chromebook)" + select BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc new file mode 100644 index 0000000..de33112 --- /dev/null +++ b/src/mainboard/google/cheza/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += memlayout.ld +bootblock-y += chromeos.c +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/cheza/board_info.txt new file mode 100644 index 0000000..5498070 --- /dev/null +++ b/src/mainboard/google/cheza/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cheza Qualcomm reference board +Category: eval +ROM protocol: QSPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c new file mode 100644 index 0000000..aceb61b --- /dev/null +++ b/src/mainboard/google/cheza/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_early_init(void) +{ + +} + +void bootblock_mainboard_init(void) +{ + +} diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c new file mode 100644 index 0000000..98c1285 --- /dev/null +++ b/src/mainboard/google/cheza/chromeos.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> + +int get_write_protect_state(void); +int get_recovery_mode_switch(void); + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_write_protect_state(void) +{ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd new file mode 100644 index 0000000..d00b5c0 --- /dev/null +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +FLASH@0x0 0x200000 { + WP_RO@0x0 0x000AB100 { + RO_SECTION@0x0 0x000A9100 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x80000 + FMAP@0xA0000 0x1000 + GBB@0xA1000 0x8000 + RO_FRID@0xA9000 0x100 + } + RO_VPD@0xA9100 0x2000 + } + RW_NVRAM@0xAB100 0x2000 + RW_ELOG@0xAD100 0x2000 + RW_VPD@0xAF100 0x2000 + RW_CDT@0xB1100 0x2000 + + RW_SECTION_A@0xB3100 0x8A100 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x80000 + RW_FWID_A@0x82000 0x100 + RW_DDR_TRAINING_A@0x82100 0x4000 + RW_XBL_BUFFER_A@0x86100 0x4000 + } + RW_SHARED@0x13D200 0x1000 { + SHARED_DATA@0x0 0x1000 + } + RW_SECTION_B@0x13E200 0x8A100 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x80000 + RW_FWID_B@0x82000 0x100 + RW_DDR_TRAINING_B@0x82100 0x4000 + RW_XBL_BUFFER_B@0x86100 0x4000 + } +} diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb new file mode 100644 index 0000000..41942f1 --- /dev/null +++ b/src/mainboard/google/cheza/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/qualcomm/sdm845 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c new file mode 100644 index 0000000..6a3fad9 --- /dev/null +++ b/src/mainboard/google/cheza/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <bootblock_common.h> + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld new file mode 100644 index 0000000..1ae10a5 --- /dev/null +++ b/src/mainboard/google/cheza/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include <soc/memlayout.ld> diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c new file mode 100644 index 0000000..8f25898 --- /dev/null +++ b/src/mainboard/google/cheza/romstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/exception.h> +#include <cbmem.h> +#include <program_loading.h> + +void main(void) +{ + exception_init(); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig new file mode 100644 index 0000000..747052e --- /dev/null +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_QUALCOMM_SDM845 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + +if SOC_QUALCOMM_SDM845 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc new file mode 100644 index 0000000..1d76649 --- /dev/null +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += i2c.c + +################################################################################ +verstage-y += stage_entry.c +verstage-y += timer.c +verstage-y += spi.c +verstage-y += i2c.c + +################################################################################ +romstage-y += stage_entry.c +romstage-y += timer.c +romstage-y += spi.c +romstage-y += cbmem.c +romstage-y += i2c.c + +################################################################################ +ramstage-y += stage_entry.c +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += cbmem.c +ramstage-y += i2c.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c new file mode 100644 index 0000000..3440dd7 --- /dev/null +++ b/src/soc/qualcomm/sdm845/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <string.h> + +extern u8 _bss[], _ebss[]; + +void bootblock_soc_early_init(void) +{ + memset(_bss, 0, (_ebss-_bss)); +} + +void bootblock_soc_init(void) +{ + +} diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c new file mode 100644 index 0000000..45cda8f --- /dev/null +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return NULL; +} diff --git a/src/soc/qualcomm/sdm845/i2c.c b/src/soc/qualcomm/sdm845/i2c.c new file mode 100644 index 0000000..586cd4e --- /dev/null +++ b/src/soc/qualcomm/sdm845/i2c.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/i2c_simple.h> + +int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, + int seg_count) +{ + return 0; +} + diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h new file mode 100644 index 0000000..9b2a0f4 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_ +#define _SOC_QUALCOMM_SDM845_GPIO_H_ + +#include <types.h> + +typedef u32 gpio_t; + +#endif // _SOC_QUALCOMM_SDM845_GPIO_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld new file mode 100644 index 0000000..a81df2c --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +#define SRAM_XBL_START(addr) SYMBOL(xbl, addr) +#define SRAM_XBL_END(addr) SYMBOL(exbl, addr) + +#define SRAM2_START(addr) SYMBOL(sram2, addr) +#define SRAM2_END(addr) SYMBOL(esram2, addr) + +#define SRAM3_START(addr) SYMBOL(sram3, addr) +#define SRAM3_END(addr) SYMBOL(esram3, addr) + +#define SRAM4_START(addr) SYMBOL(sram4, addr) +#define SRAM4_END(addr) SYMBOL(esram4, addr) + +// SYSTEM_IMEM : 0x14680000 - 0x146C0000 +// BOOT_IMEM : 0x14800000 - 0x14980000 + +SECTIONS +{ + SRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 95K) + SRAM_END(0x1469FC00) + + SRAM2_START(0x146A0000) + // This area, used by other firmware in system + SRAM2_END(0x146C0000) + + SRAM3_START(0x14800000) + // This area, contains PBL shared data & mmu non-cacheable areas + SRAM3_END(0x14816000) + + SRAM4_START(0x14816000) + BOOTBLOCK(0x14816000, 32K) + TTB(0x1481E000, 64K) + VBOOT2_WORK(0x1482E000, 16K) + STACK(0x14832000, 16K) + TIMESTAMP(0x14836000, 1K) + PRERAM_CBMEM_CONSOLE(0x14836400, 32K) + PRERAM_CBFS_CACHE(0x1483E400, 70K) + SRAM_XBL_START(0x1484FC00) + // size available is 1217KB + // qclib.elf starts at 0x148F2000, 512KB + // dcb.elf starts at 0x14972000, 8KB + // pmic.elf starts at 0x14974000, 48KB + SRAM_XBL_END(0x14980000) + SRAM4_END(0x14980000) + + DRAM_START(0x80000000) + RAMSTAGE(0x80800000, 128K) + SYMBOL(memlayout_cbmem_top, 0xA1000000) + POSTRAM_CBFS_CACHE(0xA1000000, 384K) +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c new file mode 100644 index 0000000..9f2fbc4 --- /dev/null +++ b/src/soc/qualcomm/sdm845/soc.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void soc_read_resources(device_t dev) +{ + +} + +static void soc_init(device_t dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sdm845_ops = { + CHIP_NAME("SOC Qualcomm SDM845") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c new file mode 100644 index 0000000..175b6cf --- /dev/null +++ b/src/soc/qualcomm/sdm845/spi.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + return 0; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + return 0; +} + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sdm845/stage_entry.c b/src/soc/qualcomm/sdm845/stage_entry.c new file mode 100644 index 0000000..4cfa9bd --- /dev/null +++ b/src/soc/qualcomm/sdm845/stage_entry.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <string.h> + +extern u8 _bss[], _ebss[]; +extern void main(void); +void stage_entry(void); + +void stage_entry(void) +{ + memset(_bss, 0, (_ebss-_bss)); + main(); +} diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c new file mode 100644 index 0000000..b1df161 --- /dev/null +++ b/src/soc/qualcomm/sdm845/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <delay.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + +} + +void init_timer(void) +{ + +} -- To view, visit https://review.coreboot.org/23875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I51c28455987f042e6b64a572ec2787947f29bb99 Gerrit-Change-Number: 23875 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)qualcomm.corp-partner.google.com>

1 0

Change in coreboot[master]: mainboard/google/zoombini: consolidate SPD makefiles
by build bot (Jenkins) (Code Review) Feb. 26, 2018

Feb. 26, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23874 ) Change subject: mainboard/google/zoombini: consolidate SPD makefiles ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67952/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22432/ : SUCCESS -- To view, visit https://review.coreboot.org/23874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Gerrit-Change-Number: 23874 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 21:41:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/google/zoombini: consolidate SPD makefiles
by Nick Vaccaro (Code Review) Feb. 26, 2018

Feb. 26, 2018

Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23874 to look at the new patch set (#2). Change subject: mainboard/google/zoombini: consolidate SPD makefiles ...................................................................... mainboard/google/zoombini: consolidate SPD makefiles - consolidate commonality in meowth and zoombini's SPD makefiles into a common zoombini/spd/Makefile.inc - move all SPD hex files into zoombini/spd directory - move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc BUG=b:69011806,b:71776625 BRANCH=master TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot' compile and boot successfully. Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Signed-off-by: Nick Vaccaro <nvaccaro(a)chromium.org> --- M src/mainboard/google/zoombini/Makefile.inc R src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex R src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex R src/mainboard/google/zoombini/spd/Makefile.inc R src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex R src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex R src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex R src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex M src/mainboard/google/zoombini/variants/meowth/Makefile.inc D src/mainboard/google/zoombini/variants/meowth/spd/Makefile.inc A src/mainboard/google/zoombini/variants/zoombini/Makefile.inc D src/mainboard/google/zoombini/variants/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex 12 files changed, 33 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/23874/2 -- To view, visit https://review.coreboot.org/23874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Gerrit-Change-Number: 23874 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mainboard/google/zoombini: consolidate SPD makefiles
by build bot (Jenkins) (Code Review) Feb. 26, 2018

Feb. 26, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23874 ) Change subject: mainboard/google/zoombini: consolidate SPD makefiles ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67951/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22431/ : SUCCESS -- To view, visit https://review.coreboot.org/23874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Gerrit-Change-Number: 23874 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 21:31:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/google/zoombini: consolidate SPD makefiles
by Nick Vaccaro (Code Review) Feb. 26, 2018

Feb. 26, 2018

Hello Nick Vaccaro, I'd like you to do a code review. Please visit https://review.coreboot.org/23874 to review the following change. Change subject: mainboard/google/zoombini: consolidate SPD makefiles ...................................................................... mainboard/google/zoombini: consolidate SPD makefiles - consolidate commonality in meowth and zoombini's SPD makefiles into a common zoombini/spd/Makefile.inc - move all SPD hex files into zoombini/spd directory - move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc BUG=b:69011806,b:71776625 BRANCH=master TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot' compile and boot successfully. Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Signed-off-by: Nick Vaccaro <nvaccaro(a)chromium.org> --- M src/mainboard/google/zoombini/Makefile.inc R src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex R src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex A src/mainboard/google/zoombini/spd/Makefile.inc R src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex R src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex R src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex R src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex M src/mainboard/google/zoombini/variants/meowth/Makefile.inc D src/mainboard/google/zoombini/variants/meowth/spd/Makefile.inc A src/mainboard/google/zoombini/variants/zoombini/Makefile.inc D src/mainboard/google/zoombini/variants/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex D src/mainboard/google/zoombini/variants/zoombini/spd/Makefile.inc 13 files changed, 29 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/23874/1 diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc index e4a036d..b1e31b4 100644 --- a/src/mainboard/google/zoombini/Makefile.inc +++ b/src/mainboard/google/zoombini/Makefile.inc @@ -38,3 +38,5 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include subdirs-y += variants/$(VARIANT_DIR)/spd + +subdirs-y += spd diff --git a/src/mainboard/google/zoombini/variants/meowth/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex b/src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex similarity index 100% rename from src/mainboard/google/zoombini/variants/meowth/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex rename to src/mainboard/google/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex diff --git a/src/mainboard/google/zoombini/variants/meowth/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex b/src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex similarity index 100% rename from src/mainboard/google/zoombini/variants/meowth/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex rename to src/mainboard/google/zoombini/spd/Hynix_H9HCNNNCPUMLHR_4GB.spd.hex diff --git a/src/mainboard/google/zoombini/spd/Makefile.inc b/src/mainboard/google/zoombini/spd/Makefile.inc new file mode 100644 index 0000000..b73ddd2 --- /dev/null +++ b/src/mainboard/google/zoombini/spd/Makefile.inc @@ -0,0 +1,19 @@ +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/zoombini/variants/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex b/src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex similarity index 100% rename from src/mainboard/google/zoombini/variants/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex rename to src/mainboard/google/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex diff --git a/src/mainboard/google/zoombini/variants/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex b/src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex similarity index 100% rename from src/mainboard/google/zoombini/variants/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex rename to src/mainboard/google/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex diff --git a/src/mainboard/google/zoombini/variants/meowth/spd/Samsung_K4F6E3S4HM_2GB.spd.hex b/src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex similarity index 100% rename from src/mainboard/google/zoombini/variants/meowth/spd/Samsung_K4F6E3S4HM_2GB.spd.hex rename to src/mainboard/google/zoombini/spd/Samsung_K4F6E3S4HM_2GB.spd.hex diff --git a/src/mainboard/google/zoombini/variants/meowth/spd/Samsung_K4F8E304HB_1GB.spd.hex b/src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex similarity index 100% rename from src/mainboard/google/zoombini/variants/meowth/spd/Samsung_K4F8E304HB_1GB.spd.hex rename to src/mainboard/google/zoombini/spd/Samsung_K4F8E304HB_1GB.spd.hex diff --git a/src/mainboard/google/zoombini/variants/meowth/Makefile.inc b/src/mainboard/google/zoombini/variants/meowth/Makefile.inc index 51ebbad..487bc44 100644 --- a/src/mainboard/google/zoombini/variants/meowth/Makefile.inc +++ b/src/mainboard/google/zoombini/variants/meowth/Makefile.inc @@ -13,6 +13,11 @@ ## GNU General Public License for more details. ## +SPD_SOURCES = Samsung_K4F8E304HB_1GB # 0b000 +SPD_SOURCES += Hynix_H9HCNNN8KUMLHR_1GB # 0b001 +SPD_SOURCES += Samsung_K4F6E3S4HM_2GB # 0b010 +SPD_SOURCES += Hynix_H9HCNNNCPUMLHR_4GB # 0b011 + bootblock-y += gpio.c romstage-y += memory.c diff --git a/src/mainboard/google/zoombini/variants/meowth/spd/Makefile.inc b/src/mainboard/google/zoombini/variants/meowth/spd/Makefile.inc deleted file mode 100644 index a4a7955..0000000 --- a/src/mainboard/google/zoombini/variants/meowth/spd/Makefile.inc +++ /dev/null @@ -1,40 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2017 Google Inc. -## Copyright (C) 2017 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = Samsung_K4F8E304HB_1GB # 0b000 -SPD_SOURCES += Hynix_H9HCNNN8KUMLHR_1GB # 0b001 -SPD_SOURCES += Samsung_K4F6E3S4HM_2GB # 0b010 -SPD_SOURCES += Hynix_H9HCNNNCPUMLHR_4GB # 0b011 - -ifeq ($(SPD_SOURCES),) - SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/meowth/spd/$(f).spd.hex) -endif - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc b/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc new file mode 100644 index 0000000..6007e12 --- /dev/null +++ b/src/mainboard/google/zoombini/variants/zoombini/Makefile.inc @@ -0,0 +1,3 @@ +SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_1GB # 0b000 +SPD_SOURCES += Micron_MT53B512M32D2_2GB # 0b001 +SPD_SOURCES += Micron_MT53B1024M32D4_4GB # 0b010 diff --git a/src/mainboard/google/zoombini/variants/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex b/src/mainboard/google/zoombini/variants/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex deleted file mode 100644 index 7b13b4d..0000000 --- a/src/mainboard/google/zoombini/variants/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 10 0E 15 19 05 08 00 40 00 00 02 22 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 CF D0 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zoombini/variants/zoombini/spd/Makefile.inc b/src/mainboard/google/zoombini/variants/zoombini/spd/Makefile.inc deleted file mode 100644 index a0bf3e3..0000000 --- a/src/mainboard/google/zoombini/variants/zoombini/spd/Makefile.inc +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2017 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_1GB # 0b000 -SPD_SOURCES += Micron_MT53B512M32D2_2GB # 0b001 -SPD_SOURCES += Micron_MT53B1024M32D4_4GB # 0b010 - -ifeq ($(SPD_SOURCES),) - SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/zoombini/spd/$(f).spd.hex) -endif - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd -- To view, visit https://review.coreboot.org/23874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Gerrit-Change-Number: 23874 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nami: Enable elan touchscreen
by Furquan Shaikh (Code Review) Feb. 26, 2018

Feb. 26, 2018

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/23872 ) Change subject: mb/google/poppy/variants/nami: Enable elan touchscreen ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/23872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09 Gerrit-Change-Number: 23872 Gerrit-PatchSet: 2 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 20:46:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: [WIP]mb/octopus: Add gpio configs for communities
by build bot (Jenkins) (Code Review) Feb. 26, 2018

Feb. 26, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23799 ) Change subject: [WIP]mb/octopus: Add gpio configs for communities ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67949/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22429/ : SUCCESS -- To view, visit https://review.coreboot.org/23799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Gerrit-Change-Number: 23799 Gerrit-PatchSet: 6 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 19:20:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/vboot: Add boot mode selection
by build bot (Jenkins) (Code Review) Feb. 26, 2018

Feb. 26, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23756 ) Change subject: security/vboot: Add boot mode selection ...................................................................... Patch Set 22: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67950/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22430/ : SUCCESS -- To view, visit https://review.coreboot.org/23756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43d233d5a8766af2dd7f07cc0b64293a80d5d7d2 Gerrit-Change-Number: 23756 Gerrit-PatchSet: 22 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 19:15:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/vboot: Make vboot first class citizen
by build bot (Jenkins) (Code Review) Feb. 26, 2018

Feb. 26, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23873 ) Change subject: security/vboot: Make vboot first class citizen ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67948/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22428/ : SUCCESS -- To view, visit https://review.coreboot.org/23873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If1ac6db16647eba4ddb28b74d1e0501224c841df Gerrit-Change-Number: 23873 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Feb 2018 18:44:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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