coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/fizz: Set Pmax to 120 for all SKUs
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23633 ) Change subject: mb/google/fizz: Set Pmax to 120 for all SKUs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67138/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21702/ : SUCCESS -- To view, visit https://review.coreboot.org/23633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Gerrit-Change-Number: 23633 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 05:24:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig...
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23591 ) Change subject: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for CNP-PCH ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67136/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21701/ : SUCCESS -- To view, visit https://review.coreboot.org/23591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Gerrit-Change-Number: 23591 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 05:24:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/fizz: Set Pmax to 120 for all SKUs
by Furquan Shaikh (Code Review) 07 Feb '18

07 Feb '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/23633 ) Change subject: mb/google/fizz: Set Pmax to 120 for all SKUs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/23633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Gerrit-Change-Number: 23633 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 07 Feb 2018 05:20:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/fizz: Set Pmax to 120 for all SKUs
by Shelley Chen (Code Review) 07 Feb '18

07 Feb '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/23633 Change subject: mb/google/fizz: Set Pmax to 120 for all SKUs ...................................................................... mb/google/fizz: Set Pmax to 120 for all SKUs BUG=b:71594855 BRANCH=None TEST=Make sure correct pmax value is being passed into fsp Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/23633/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 9fb366d..3b084ff 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -285,6 +285,7 @@ register "speed_shift_enable" = "1" register "tdp_psyspl2" = "90" + register "psys_pmax" = "120" register "tcc_offset" = "6" # TCC of 94C # Use default SD card detect GPIO configuration -- To view, visit https://review.coreboot.org/23633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Gerrit-Change-Number: 23633 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23621 ) Change subject: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67135/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21699/ : SUCCESS -- To view, visit https://review.coreboot.org/23621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Gerrit-Change-Number: 23621 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 05:08:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23632 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67134/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21698/ : SUCCESS -- To view, visit https://review.coreboot.org/23632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba99bb8ce192b2d05cff7d2cae47df40f8724127 Gerrit-Change-Number: 23632 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 03:17:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23631 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67133/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21697/ : SUCCESS -- To view, visit https://review.coreboot.org/23631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e3a026425532d03fe158760438d2b6030ad8fa7 Gerrit-Change-Number: 23631 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 03:17:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by Robert Reeves (Code Review) 07 Feb '18

07 Feb '18

Robert Reeves has uploaded this change for review. ( https://review.coreboot.org/23632 Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... mainboard/hp: Add HP Elitebook 8770w This is based on the code from the 8470p port. Tested on the quad core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics cards. Tested working with both Quadro K3000M and GTX 980M 8GB. Tested and working: - memory: 4G+4G+4G+4G - Linux (Debian Stretch with kernel 4.9.0) boot from SeaBIOS payload with graphics init disabled in coreboot. I allow SeaBIOS to load the VBIOS from the MXM. - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - VGA - Displayport - Audio - S3 with SeaBIOS 1.10.3, not working with 1.11 - Brightness and volume FN keys Change-Id: Iba99bb8ce192b2d05cff7d2cae47df40f8724127 Signed-off-by: xiinc37 <xiinc37(a)gmail.com> --- M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/8770w/board_info.txt M src/mainboard/hp/8770w/cmos.layout M src/mainboard/hp/8770w/devicetree.cb M src/mainboard/hp/8770w/gpio.c M src/mainboard/hp/8770w/hda_verb.c M src/mainboard/hp/8770w/mainboard.c M src/mainboard/hp/8770w/romstage.c 8 files changed, 59 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/23632/1 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 2157867..c650309 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -13,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_HP_8470P +if BOARD_HP_8770W config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -23,13 +24,10 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS select EC_HP_KBC1126 select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE @@ -45,23 +43,15 @@ config MAINBOARD_DIR string - default hp/8470p + default hp/8770w config MAINBOARD_PART_NUMBER string - default "EliteBook 8470p" - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config VGA_BIOS_ID - string - default "8086,0166" + default "EliteBook 8770w" config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x179b + default 0x176c config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt index 1d0ca8b..0d04ad0 100644 --- a/src/mainboard/hp/8770w/board_info.txt +++ b/src/mainboard/hp/8770w/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/… ROM protocol: SPI ROM package: SOIC-16 ROM socketed: n diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout index f55fbd5..69d2767 100644 --- a/src/mainboard/hp/8770w/cmos.layout +++ b/src/mainboard/hp/8770w/cmos.layout @@ -3,6 +3,7 @@ ## ## Copyright (C) 2007-2008 coresystems GmbH ## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2018 Robert Reeves ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -64,7 +65,6 @@ #424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size #435 5 r 0 unused 440 8 h 0 volume @@ -88,27 +88,20 @@ 2 1 Disable 4 0 Fallback 4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew 7 0 Disable 7 1 Enable 7 2 Keep 9 0 AHCI 9 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index b7254bb..2f2a5e0 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,21 +16,6 @@ # chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.link_frequency_270_mhz" = "1" - register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000385" - register "gpu_dp_b_hotplug" = "4" - register "gpu_dp_c_hotplug" = "4" - register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" - register "gpu_panel_power_backlight_off_delay" = "2000" - register "gpu_panel_power_backlight_on_delay" = "2000" - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_down_delay" = "230" - register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on @@ -48,15 +34,15 @@ end device domain 0x0 on device pci 00.0 on # Host bridge - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 01.0 on # PCIe Bridge for discrete graphics end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x179b + device pci 02.0 off # Internal graphics VGA controller + subsystemid 0x103c 0x176c end - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x007c0201" @@ -68,7 +54,7 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x3b" + register "sata_port_map" = "0x1f" register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" @@ -77,40 +63,40 @@ register "spi_lvscc" = "0" device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 16.1 off # Management Engine Interface 2 end device pci 16.2 off # Management Engine IDE-R end device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end - device pci 1c.1 on # PCIe Port #2, ExpressCard - subsystemid 0x103c 0x179b + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x176c end - device pci 1c.2 on # PCIe Port #3, SD/MMC - subsystemid 0x103c 0x179b + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x176c end - device pci 1c.3 on # PCIe Port #4, WLAN - subsystemid 0x103c 0x179b + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x176c end - device pci 1c.4 off # PCIe Port #5 + device pci 1c.4 on # PCIe Port #5 end device pci 1c.5 off # PCIe Port #6 end @@ -119,12 +105,12 @@ device pci 1c.7 off # PCIe Port #8 end device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1e.0 off # PCI bridge end device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -146,7 +132,7 @@ end #chip superio/smsc/lpc47n217 end device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1f.3 off # SMBus end diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c index 768af5c..ac054d9 100644 --- a/src/mainboard/hp/8770w/gpio.c +++ b/src/mainboard/hp/8770w/gpio.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -18,7 +19,7 @@ #include <southbridge/intel/common/gpio.h> static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, + .gpio0 = GPIO_MODE_NATIVE, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -32,28 +33,27 @@ .gpio11 = GPIO_MODE_GPIO, .gpio12 = GPIO_MODE_NATIVE, .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, .gpio15 = GPIO_MODE_GPIO, .gpio16 = GPIO_MODE_GPIO, .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, .gpio22 = GPIO_MODE_GPIO, .gpio23 = GPIO_MODE_GPIO, .gpio24 = GPIO_MODE_GPIO, .gpio25 = GPIO_MODE_NATIVE, .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_NATIVE, .gpio29 = GPIO_MODE_GPIO, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_NATIVE, }; static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, .gpio3 = GPIO_DIR_INPUT, @@ -64,29 +64,23 @@ .gpio10 = GPIO_DIR_INPUT, .gpio11 = GPIO_DIR_OUTPUT, .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, .gpio15 = GPIO_DIR_INPUT, .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_OUTPUT, - .gpio21 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_OUTPUT, .gpio23 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_OUTPUT, .gpio29 = GPIO_DIR_OUTPUT, }; static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, .gpio8 = GPIO_LEVEL_LOW, .gpio11 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_HIGH, .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, .gpio29 = GPIO_LEVEL_HIGH, }; @@ -102,7 +96,6 @@ .gpio7 = GPIO_INVERT, .gpio10 = GPIO_INVERT, .gpio13 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, }; static const struct pch_gpio_set1 pch_gpio_set1_blink = { @@ -112,9 +105,9 @@ .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_GPIO, - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, .gpio38 = GPIO_MODE_GPIO, .gpio39 = GPIO_MODE_GPIO, .gpio40 = GPIO_MODE_NATIVE, @@ -126,7 +119,7 @@ .gpio46 = GPIO_MODE_GPIO, .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_GPIO, - .gpio49 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, .gpio50 = GPIO_MODE_GPIO, .gpio51 = GPIO_MODE_GPIO, .gpio52 = GPIO_MODE_GPIO, @@ -146,15 +139,11 @@ static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_OUTPUT, - .gpio37 = GPIO_DIR_OUTPUT, .gpio38 = GPIO_DIR_INPUT, .gpio39 = GPIO_DIR_INPUT, .gpio44 = GPIO_DIR_INPUT, .gpio46 = GPIO_DIR_OUTPUT, .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_OUTPUT, .gpio50 = GPIO_DIR_INPUT, .gpio51 = GPIO_DIR_INPUT, .gpio52 = GPIO_DIR_INPUT, @@ -168,11 +157,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, .gpio46 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio57 = GPIO_LEVEL_HIGH, .gpio60 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c index 0d7389a..51869cb 100644 --- a/src/mainboard/hp/8770w/hda_verb.c +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -4,6 +4,7 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,11 +20,11 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c17c2, /* Subsystem ID */ + 0x103c176c, /* Subsystem ID */ 0x0000000b, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x103c17c2), + AZALIA_SUBVENDOR(0x0, 0x103c176c), /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), @@ -54,21 +55,6 @@ /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - - 0x00000004, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ - AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c index b5fdecc..9e2634f 100644 --- a/src/mainboard/hp/8770w/mainboard.c +++ b/src/mainboard/hp/8770w/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,13 +15,10 @@ */ #include <device/device.h> -#include <drivers/intel/gma/int15.h> static void mainboard_enable(device_t dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index bb9298c..f00c6f2 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -37,8 +38,9 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } -void mainboard_rcba_config(void) +void rcba_config(void) { + RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -76,5 +78,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); } -- To view, visit https://review.coreboot.org/23632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iba99bb8ce192b2d05cff7d2cae47df40f8724127 Gerrit-Change-Number: 23632 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com>

1 0

Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by Robert Reeves (Code Review) 07 Feb '18

07 Feb '18

Robert Reeves has uploaded this change for review. ( https://review.coreboot.org/23631 Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... mainboard/hp: Add HP Elitebook 8770w Code copied from the 8470p port. Change-Id: I6e3a026425532d03fe158760438d2b6030ad8fa7 Signed-off-by: xiinc37 <xiinc37(a)gmail.com> --- A src/mainboard/hp/8770w/Kconfig A src/mainboard/hp/8770w/Kconfig.name A src/mainboard/hp/8770w/Makefile.inc A src/mainboard/hp/8770w/acpi/ec.asl A src/mainboard/hp/8770w/acpi/platform.asl A src/mainboard/hp/8770w/acpi/superio.asl A src/mainboard/hp/8770w/acpi_tables.c A src/mainboard/hp/8770w/board_info.txt A src/mainboard/hp/8770w/cmos.default A src/mainboard/hp/8770w/cmos.layout A src/mainboard/hp/8770w/devicetree.cb A src/mainboard/hp/8770w/dsdt.asl A src/mainboard/hp/8770w/gpio.c A src/mainboard/hp/8770w/hda_verb.c A src/mainboard/hp/8770w/mainboard.c A src/mainboard/hp/8770w/romstage.c 16 files changed, 949 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/23631/1 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig new file mode 100644 index 0000000..2157867 --- /dev/null +++ b/src/mainboard/hp/8770w/Kconfig @@ -0,0 +1,78 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_HP_8470P + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_SOCKET_RPGA989 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select EC_HP_KBC1126 + select SUPERIO_SMSC_LPC47N217 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/8470p + +config MAINBOARD_PART_NUMBER + string + default "EliteBook 8470p" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x179b + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif diff --git a/src/mainboard/hp/8770w/Kconfig.name b/src/mainboard/hp/8770w/Kconfig.name new file mode 100644 index 0000000..df9981c --- /dev/null +++ b/src/mainboard/hp/8770w/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_8770W + bool "EliteBook 8770w" diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc new file mode 100644 index 0000000..7a00cce --- /dev/null +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8770w/acpi/ec.asl b/src/mainboard/hp/8770w/acpi/ec.asl new file mode 100644 index 0000000..ac65fb3 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi/ec.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/8770w/acpi/platform.asl b/src/mainboard/hp/8770w/acpi/platform.asl new file mode 100644 index 0000000..fe0f936 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi/platform.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/8770w/acpi/superio.asl b/src/mainboard/hp/8770w/acpi/superio.asl new file mode 100644 index 0000000..b3ea115 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/8770w/acpi_tables.c b/src/mainboard/hp/8770w/acpi_tables.c new file mode 100644 index 0000000..d8d89e4 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt new file mode 100644 index 0000000..1d0ca8b --- /dev/null +++ b/src/mainboard/hp/8770w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 +ROM protocol: SPI +ROM package: SOIC-16 +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/hp/8770w/cmos.default b/src/mainboard/hp/8770w/cmos.default new file mode 100644 index 0000000..fcbe0fb --- /dev/null +++ b/src/mainboard/hp/8770w/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +sata_mode=AHCI diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout new file mode 100644 index 0000000..f55fbd5 --- /dev/null +++ b/src/mainboard/hp/8770w/cmos.layout @@ -0,0 +1,116 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 5 r 0 unused + +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb new file mode 100644 index 0000000..b7254bb --- /dev/null +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -0,0 +1,159 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000385" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x0d9c0d9c" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x179b + end + device pci 01.0 on # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x179b + end + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3b" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x103c 0x179b + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x179b + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x103c 0x179b + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x179b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x179b + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x179b + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x179b + end + device pci 1c.1 on # PCIe Port #2, ExpressCard + subsystemid 0x103c 0x179b + end + device pci 1c.2 on # PCIe Port #3, SD/MMC + subsystemid 0x103c 0x179b + end + device pci 1c.3 on # PCIe Port #4, WLAN + subsystemid 0x103c 0x179b + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x179b + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x179b + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end # kbc1126 + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off # Com2 + end + end #chip superio/smsc/lpc47n217 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x179b + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl new file mode 100644 index 0000000..51934c7 --- /dev/null +++ b/src/mainboard/hp/8770w/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c new file mode 100644 index 0000000..768af5c --- /dev/null +++ b/src/mainboard/hp/8770w/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c new file mode 100644 index 0000000..0d7389a --- /dev/null +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c17c2, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c17c2), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c new file mode 100644 index 0000000..b5fdecc --- /dev/null +++ b/src/mainboard/hp/8770w/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c new file mode 100644 index 0000000..bb9298c --- /dev/null +++ b/src/mainboard/hp/8770w/romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +void pch_enable_lpc(void) +{ + /* + * CNF2 and CNF1 for Super I/O + * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC + * Enable parallel port and serial port + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + LPT_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 0, 0, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/23631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6e3a026425532d03fe158760438d2b6030ad8fa7 Gerrit-Change-Number: 23631 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com>

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by Robert Reeves (Code Review) 07 Feb '18

07 Feb '18

Robert Reeves has abandoned this change. ( https://review.coreboot.org/23628 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Abandoned Made mistake while making commit. -- To view, visit https://review.coreboot.org/23628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I70477cfa314ed607b41b9096bc1b8664eff6baf0 Gerrit-Change-Number: 23628 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit February 2018