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Change in coreboot[master]: soc/intel/skylake: Clean up SMBIOS Table Type 17 creation
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23636
) Change subject: soc/intel/skylake: Clean up SMBIOS Table Type 17 creation ...................................................................... Patch Set 1: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67154/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/21718/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Gerrit-Change-Number: 23636 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 09:41:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/skylake: Clean up SMBIOS Table Type 17 creation
by Subrata Banik (Code Review)
07 Feb '18
07 Feb '18
Subrata Banik has uploaded this change for review. (
https://review.coreboot.org/23636
Change subject: soc/intel/skylake: Clean up SMBIOS Table Type 17 creation ...................................................................... soc/intel/skylake: Clean up SMBIOS Table Type 17 creation Clean up skylake/kabylake SMBIOS Type 17 table as per Cannonlake review feedback. Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/23636/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index d4606a4..98c78a5 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -44,6 +44,13 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +/* Memory Channel Present Status */ +enum { + CHANNEL_NOT_PRESENT, + CHANNEL_DISABLED, + CHANNEL_PRESENT +}; + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -56,13 +63,14 @@ struct dimm_info *dest_dimm; struct memory_info *mem_info; const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; /* Locate the memory info HOB, presence validated by raminit */ memory_info_hob = fsp_find_extension_hob_by_guid(smbios_memory_info_guid, &hob_size); - if (memory_info_hob == NULL) { + if (memory_info_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } @@ -84,7 +92,7 @@ ctrlr_info = &memory_info_hob->Controller[0]; for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { channel_info = &ctrlr_info->ChannelInfo[channel]; - if (channel_info->Status != 2) + if (channel_info->Status != CHANNEL_PRESENT) continue; for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { src_dimm = &channel_info->DimmInfo[dimm]; -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Gerrit-Change-Number: 23636 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
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Change in coreboot[master]: mb/google/poppy/variants/nami: Revise AC/DC loadlines
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23635
) Change subject: mb/google/poppy/variants/nami: Revise AC/DC loadlines ...................................................................... Patch Set 1: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67153/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/21717/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Gerrit-Change-Number: 23635 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 09:31:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: mb/google/poppy/variants/nami: Revise AC/DC loadlines
by Gaggery Tsai (Code Review)
07 Feb '18
07 Feb '18
Gaggery Tsai has uploaded this change for review. (
https://review.coreboot.org/23635
Change subject: mb/google/poppy/variants/nami: Revise AC/DC loadlines ...................................................................... mb/google/poppy/variants/nami: Revise AC/DC loadlines This patch revises AC/DC loadlines from VRTT reports attached in b/72129954. +----------------+-------+-------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------+-------+-------+-------+ | AcLoadline | 11 | 2.4 | 3.1 | 3.1 | | DcLoadline | 10 | 2.46 | 3.1 | 3.1 | +----------------+-------+-------+-------+-------+ BUG=b:72351128 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings are passed to FSP. Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23635/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 348f7de..60103ae 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -78,8 +78,8 @@ #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | - #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | + #| AcLoadline | 11 | 2.4 | 3.1 | 3.1 | + #| DcLoadline | 10 | 2.46 | 3.1 | 3.1 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, @@ -91,8 +91,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 1500, - .dc_loadline = 1430, + .ac_loadline = 1100, + .dc_loadline = 1000, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -105,8 +105,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 483, + .ac_loadline = 240, + .dc_loadline = 246, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -119,8 +119,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 550, - .dc_loadline = 420, + .ac_loadline = 310, + .dc_loadline = 310, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -133,8 +133,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 550, - .dc_loadline = 420, + .ac_loadline = 310, + .dc_loadline = 310, }" # Root port 4 (x1) -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Gerrit-Change-Number: 23635 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>
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Change in coreboot[master]: mb/intel/kblrvp: Enable Kabylake RVP8
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23383
) Change subject: mb/intel/kblrvp: Enable Kabylake RVP8 ...................................................................... Patch Set 8: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67152/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/21716/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed Gerrit-Change-Number: 23383 Gerrit-PatchSet: 8 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 07:13:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/common/block: Fix SATA chipset register definitions anomalies
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23589
) Change subject: soc/intel/common/block: Fix SATA chipset register definitions anomalies ...................................................................... Patch Set 7: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67151/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/21713/
: SUCCESS -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Gerrit-Change-Number: 23589 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 06:57:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig...
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23591
) Change subject: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for CNP-PCH ...................................................................... Patch Set 8: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67150/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/21714/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Gerrit-Change-Number: 23591 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 06:56:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No
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Change in coreboot[master]: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23621
) Change subject: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 ...................................................................... Patch Set 5: Verified+1 Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/67149/
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https://qa.coreboot.org/job/coreboot-checkpatch/21715/
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Gerrit-Change-Number: 23621 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 06:51:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig...
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
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) Change subject: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for CNP-PCH ...................................................................... Patch Set 7: Verified-1 Build Failed
https://qa.coreboot.org/job/coreboot-gerrit/67148/
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Change in coreboot[master]: soc/intel/common/block: Fix SATA chipset register definitions anomalies
by build bot (Jenkins) (Code Review)
07 Feb '18
07 Feb '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/23589
) Change subject: soc/intel/common/block: Fix SATA chipset register definitions anomalies ...................................................................... Patch Set 6: Verified-1 Build Failed
https://qa.coreboot.org/job/coreboot-gerrit/67147/
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