coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/google/meowth: Enable ECT back
by Lijian Zhao (Code Review) 08 Feb '18

08 Feb '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/23645 ) Change subject: mainboard/google/meowth: Enable ECT back ...................................................................... Patch Set 1: Another thought is we can simply remove the override line in memory.c under both Zoombini and Meowth -- To view, visit https://review.coreboot.org/23645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Gerrit-Change-Number: 23645 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 01:16:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/meowth: Enable ECT back
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23645 ) Change subject: mainboard/google/meowth: Enable ECT back ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67179/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21735/ : SUCCESS -- To view, visit https://review.coreboot.org/23645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Gerrit-Change-Number: 23645 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 01:12:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: Enable ECT back
by Lijian Zhao (Code Review) 08 Feb '18

08 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23645 Change subject: mainboard/google/meowth: Enable ECT back ...................................................................... mainboard/google/meowth: Enable ECT back Previously ECT had been disabled during meowth P0 bring up, on D0 stepping system and FSP version 7.x.20.52, disable ECT will cause MRC training failure and stuck at post code 00D5h. BUG=b.72473063 TEST=Apply patch and build coreboot image, flash into meowth P0 system with D0 stepping silicon installed, system can pass MRC training and boot up into OS. Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/zoombini/variants/meowth/memory.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/23645/1 diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c index 7c2fa20..c72ffea 100644 --- a/src/mainboard/google/zoombini/variants/meowth/memory.c +++ b/src/mainboard/google/zoombini/variants/meowth/memory.c @@ -82,8 +82,8 @@ /* Meowth is a non-interleaved design */ .dq_pins_interleaved = 0, - /* Disable Early Command Training */ - .ect = 0, + /* Enable Early Command Training */ + .ect = 1, }; const struct lpddr4_cfg *variant_lpddr4_config(void) -- To view, visit https://review.coreboot.org/23645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Gerrit-Change-Number: 23645 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23644 ) Change subject: soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67178/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21734/ : SUCCESS -- To view, visit https://review.coreboot.org/23644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b Gerrit-Change-Number: 23644 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 00:11:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem
by Richard Spiegel (Code Review) 08 Feb '18

08 Feb '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23644 Change subject: soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem ...................................................................... soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem SMBIOS structure type 17 is not being generated because memory info is not being stored to cbmem. This has to happen after AGESA AmdInitLate has run, but before the structure is released. There's a need to convert format between AGESA generated info, and what is required in cbmem. BUG=b:65403853 TEST=build and run kahlee, verify if SMBIOS structure type 17 is being generated, and if associated strings are what should be expected. Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pi/amd_late_init.c 1 file changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/23644/1 diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 3eb3674..499931a 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -19,16 +19,113 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <cbmem.h> +#include <memory_info.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +/* + * Description Copies a string from origin to destine. However, destine buffer + * can sometimes be smaller than the string in origin. This procedure makes + * sure that at least the last characters are copied. + * + * origin pointer to origing of string. + * destin pointer to final string. + * o_size size of origin buffer. + * d_size size of destin buffer. + */ +static void string_end(char *origin, char *destin, uint8_t o_size, + uint8_t d_size) +{ + uint8_t size, i, j; + char *optr, *dptr; + + optr = origin; + dptr = destin; + if (o_size > d_size) { + /* Find the actual string size */ + i = 0; + for (j = 0; j < o_size; j++) { + if (*optr == 0) + break; + optr++; + i++; + } + i++; /* include terminator in string size */ + if (i < d_size) { + /* actual string smaller than destin buffer */ + optr = origin; + size = o_size; + } else { + /* String equal or greater than destin buffer */ + for (j = 1; j < d_size; j++) + optr--; + size = d_size; + } + } else { + size = o_size; + } + for (i = 0; i < size; i++) + dptr[i] = optr[i]; +} + +static void transfer_memory_info(TYPE17_DMI_INFO *dmi17, + struct dimm_info *dimm) +{ + dimm->dimm_size = dmi17->ExtSize; + dimm->ddr_type = dmi17->MemoryType; + dimm->ddr_frequency = dmi17->Speed; + dimm->rank_per_dimm = dmi17->Attributes; + dimm->mod_id = dmi17->DeviceLocator[5] & 0x0f; + dimm->mod_type = dmi17->MemoryType; + dimm->bus_width = dmi17->DataWidth; + dimm->bank_locator = 0; + string_end(dmi17->SerialNumber, (char *)&dimm->serial, 9, 5); + dimm->module_part_number[0] = 0x4e; /* NA */ + dimm->module_part_number[1] = 0x41; + dimm->module_part_number[2] = 0; +} + +static void prepare_dmi_17(void) +{ + DMI_INFO *DmiTable; + TYPE17_DMI_INFO *address; + struct memory_info *mem_info; + struct dimm_info *dimm; + uint8_t i, j; /* i for channel, j for dimm */ + int dimm_cnt = 0; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + if (!mem_info) { + printk(BIOS_DEBUG, "Failed to add memory info to CBMEM.\n"); + return; + } + memset(mem_info, 0, sizeof(struct memory_info)); + + DmiTable = agesawrapper_getlateinitptr(PICK_DMI); + for (i = 0; i < MAX_CHANNELS_PER_SOCKET; i++) { + for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { + address = &DmiTable->T17[0][i][j]; + if (address->Handle > 0) { + dimm = &mem_info->dimm[dimm_cnt]; + dimm->channel_num = i; + dimm->dimm_num = j; + transfer_memory_info(address, dimm); + dimm_cnt++; + } + } + } + mem_info->dimm_cnt = dimm_cnt; +} + static void agesawrapper_post_device(void *unused) { if (acpi_is_wakeup_s3()) return; do_agesawrapper(agesawrapper_amdinitlate, "amdinitlate"); + prepare_dmi_17(); if (!acpi_s3_resume_allowed()) return; -- To view, visit https://review.coreboot.org/23644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b Gerrit-Change-Number: 23644 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w (copy)
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23631 ) Change subject: mainboard/hp: Add HP Elitebook 8770w (copy) ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67177/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21733/ : SUCCESS -- To view, visit https://review.coreboot.org/23631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e3a026425532d03fe158760438d2b6030ad8fa7 Gerrit-Change-Number: 23631 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 22:49:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w (copy)
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23631 ) Change subject: mainboard/hp: Add HP Elitebook 8770w (copy) ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67176/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21732/ : SUCCESS -- To view, visit https://review.coreboot.org/23631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e3a026425532d03fe158760438d2b6030ad8fa7 Gerrit-Change-Number: 23631 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 22:21:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23632 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67175/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/21731/ : SUCCESS -- To view, visit https://review.coreboot.org/23632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba99bb8ce192b2d05cff7d2cae47df40f8724127 Gerrit-Change-Number: 23632 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 22:17:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23592 ) Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67173/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21729/ : SUCCESS -- To view, visit https://review.coreboot.org/23592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Gerrit-Change-Number: 23592 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 20:38:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common: Add S3 supporting functions
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22727 ) Change subject: soc/amd/common: Add S3 supporting functions ...................................................................... Patch Set 14: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67169/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21727/ : SUCCESS -- To view, visit https://review.coreboot.org/22727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63 Gerrit-Change-Number: 22727 Gerrit-PatchSet: 14 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Feb 2018 18:00:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit February 2018