coreboot-gerrit February 2018

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Change in coreboot[master]: src/cpu/intel: Don't hide pointers behind typedefs
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23652 ) Change subject: src/cpu/intel: Don't hide pointers behind typedefs ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67198/ : UNSTABLE -- To view, visit https://review.coreboot.org/23652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I17675b004023453f137abd387cfacd308d9b98b5 Gerrit-Change-Number: 23652 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 12:22:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/cpu/intel: Don't hide pointers behind typedefs
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23652 ) Change subject: src/cpu/intel: Don't hide pointers behind typedefs ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/21753/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/67197/ : FAILURE -- To view, visit https://review.coreboot.org/23652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I17675b004023453f137abd387cfacd308d9b98b5 Gerrit-Change-Number: 23652 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 12:17:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/cpu/intel: Don't hide pointers behind typedefs
by Elyes HAOUAS (Code Review) 08 Feb '18

08 Feb '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/23652 ) Change subject: src/cpu/intel: Don't hide pointers behind typedefs ...................................................................... src/cpu/intel: Don't hide pointers behind typedefs See Change 7146 Change-Id: I17675b004023453f137abd387cfacd308d9b98b5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/acpi.c M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/speedstep/acpi.c 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/23652/2 -- To view, visit https://review.coreboot.org/23652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I17675b004023453f137abd387cfacd308d9b98b5 Gerrit-Change-Number: 23652 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/cpu: Don't hide pointers behind typedefs
by Elyes HAOUAS (Code Review) 08 Feb '18

08 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23652 Change subject: src/cpu: Don't hide pointers behind typedefs ...................................................................... src/cpu: Don't hide pointers behind typedefs See Change 7146 Change-Id: I17675b004023453f137abd387cfacd308d9b98b5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/acpi.c M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/speedstep/acpi.c 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/23652/1 diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index 6bf30e1..a10c91b 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -298,7 +298,7 @@ acpigen_pop_len(); } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 2124386..80a56c0 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -259,7 +259,7 @@ acpigen_pop_len(); } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 74d8fba..40279bf 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -303,7 +303,7 @@ acpigen_pop_len(); } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 8d9a4dc..d680497 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -308,7 +308,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + device dev = dev_find_slot(0, PCI_DEVFN(0, 0)); printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index e64405ac..7de8b19 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -295,7 +295,7 @@ acpigen_pop_len(); } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 33c4212..8e2c0d1 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -298,7 +298,7 @@ acpigen_pop_len(); } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 73b7431..0feaa2f 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -113,7 +113,7 @@ /** * @brief Generate ACPI entries for Speedstep for each cpu */ -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); -- To view, visit https://review.coreboot.org/23652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I17675b004023453f137abd387cfacd308d9b98b5 Gerrit-Change-Number: 23652 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23651 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67196/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21752/ : SUCCESS -- To view, visit https://review.coreboot.org/23651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a Gerrit-Change-Number: 23651 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 11:40:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2....
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23650 ) Change subject: drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driver ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67195/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21751/ : SUCCESS -- To view, visit https://review.coreboot.org/23650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Gerrit-Change-Number: 23650 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 11:30:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by Robert Reeves (Code Review) 08 Feb '18

08 Feb '18

Robert Reeves has uploaded this change for review. ( https://review.coreboot.org/23651 Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... mainboard/hp: Add HP Elitebook 8770w This is based on the code from the 8470p port. Tested on the quad core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics cards. Tested working with both Quadro K3000M and GTX 980M 8GB. Tested and working: - memory: 4G+4G+4G+4G - Linux (Debian Stretch with kernel 4.9.0) boot from SeaBIOS payload with graphics init disabled in coreboot. I allow SeaBIOS to load the VBIOS from the MXM. - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - VGA - Displayport - Audio - S3 with SeaBIOS 1.10.3, not working with 1.11 - Brightness and volume FN keys Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a Signed-off-by: xiinc37 <xiinc37(a)gmail.com> --- A src/mainboard/hp/8770w/Kconfig A src/mainboard/hp/8770w/Kconfig.name A src/mainboard/hp/8770w/Makefile.inc A src/mainboard/hp/8770w/acpi/ec.asl A src/mainboard/hp/8770w/acpi/platform.asl A src/mainboard/hp/8770w/acpi/superio.asl A src/mainboard/hp/8770w/acpi_tables.c A src/mainboard/hp/8770w/board_info.txt A src/mainboard/hp/8770w/cmos.default A src/mainboard/hp/8770w/cmos.layout A src/mainboard/hp/8770w/devicetree.cb A src/mainboard/hp/8770w/dsdt.asl A src/mainboard/hp/8770w/gpio.c A src/mainboard/hp/8770w/hda_verb.c A src/mainboard/hp/8770w/mainboard.c A src/mainboard/hp/8770w/romstage.c 16 files changed, 891 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/23651/1 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig new file mode 100644 index 0000000..c650309 --- /dev/null +++ b/src/mainboard/hp/8770w/Kconfig @@ -0,0 +1,68 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# Copyright (C) 2018 Robert Reeves +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_HP_8770W + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_SOCKET_RPGA989 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select EC_HP_KBC1126 + select SUPERIO_SMSC_LPC47N217 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/8770w + +config MAINBOARD_PART_NUMBER + string + default "EliteBook 8770w" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x176c + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif diff --git a/src/mainboard/hp/8770w/Kconfig.name b/src/mainboard/hp/8770w/Kconfig.name new file mode 100644 index 0000000..df9981c --- /dev/null +++ b/src/mainboard/hp/8770w/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_8770W + bool "EliteBook 8770w" diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc new file mode 100644 index 0000000..7a00cce --- /dev/null +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8770w/acpi/ec.asl b/src/mainboard/hp/8770w/acpi/ec.asl new file mode 100644 index 0000000..ac65fb3 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi/ec.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/8770w/acpi/platform.asl b/src/mainboard/hp/8770w/acpi/platform.asl new file mode 100644 index 0000000..fe0f936 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi/platform.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/8770w/acpi/superio.asl b/src/mainboard/hp/8770w/acpi/superio.asl new file mode 100644 index 0000000..b3ea115 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/8770w/acpi_tables.c b/src/mainboard/hp/8770w/acpi_tables.c new file mode 100644 index 0000000..d8d89e4 --- /dev/null +++ b/src/mainboard/hp/8770w/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt new file mode 100644 index 0000000..0d04ad0 --- /dev/null +++ b/src/mainboard/hp/8770w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/… +ROM protocol: SPI +ROM package: SOIC-16 +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/hp/8770w/cmos.default b/src/mainboard/hp/8770w/cmos.default new file mode 100644 index 0000000..fcbe0fb --- /dev/null +++ b/src/mainboard/hp/8770w/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +sata_mode=AHCI diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout new file mode 100644 index 0000000..7b95f69 --- /dev/null +++ b/src/mainboard/hp/8770w/cmos.layout @@ -0,0 +1,109 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2018 Robert Reeves +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +#435 5 r 0 unused + +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 Compatible + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb new file mode 100644 index 0000000..a7238ac --- /dev/null +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -0,0 +1,146 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# Copyright (C) 2018 Robert Reeves +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x176c + end + device pci 01.0 on # PCIe Bridge for discrete graphics + end + device pci 02.0 off # Internal graphics VGA controller + subsystemid 0x103c 0x176c + end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1f" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x103c 0x176c + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x176c + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x103c 0x176c + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x176c + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x176c + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x176c + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x176c + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x176c + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x176c + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x176c + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x103c 0x176c + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x176c + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x176c + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end # kbc1126 + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off # Com2 + end + end #chip superio/smsc/lpc47n217 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x176c + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl new file mode 100644 index 0000000..51934c7 --- /dev/null +++ b/src/mainboard/hp/8770w/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c new file mode 100644 index 0000000..ac054d9 --- /dev/null +++ b/src/mainboard/hp/8770w/gpio.c @@ -0,0 +1,228 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Robert Reeves + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_NATIVE, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio2 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c new file mode 100644 index 0000000..51869cb --- /dev/null +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c176c, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c176c), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c new file mode 100644 index 0000000..9e2634f --- /dev/null +++ b/src/mainboard/hp/8770w/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_enable(device_t dev) +{ + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c new file mode 100644 index 0000000..9fa7e8c --- /dev/null +++ b/src/mainboard/hp/8770w/romstage.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +void pch_enable_lpc(void) +{ + /* + * CNF2 and CNF1 for Super I/O + * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC + * Enable parallel port and serial port + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + LPT_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 0, 0, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/23651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a Gerrit-Change-Number: 23651 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com>

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Change in coreboot[master]: drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2....
by Subrata Banik (Code Review) 08 Feb '18

08 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23650 Change subject: drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driver ...................................................................... drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driver As per FSP 2.0 specification and FSP SOC integration guide, its not expected that SMBIOS Memory Information GUID will be same for all platform. Hence fsp_find_smbios_memory_info() function inside common/driver code is not generic one. Removing this function and making use of fsp_find_extension_hob_by_guid() to find SMBIOS Memory Info GUID from platform code as needed. Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/denverton_ns/romstage.c 5 files changed, 81 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/23650/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index cce81f9..1e0b5c8 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -39,11 +39,6 @@ 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 }; -const uint8_t smbios_memory_info_guid[16] = { - 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, - 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 -}; - static const uint8_t uuid_fv_info[16] = { 0x2e, 0x72, 0x8e, 0x79, 0xb2, 0x15, 0x13, 0x4e, 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 @@ -304,8 +299,3 @@ { return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); } - -const void *fsp_find_smbios_memory_info(size_t *size) -{ - return fsp_find_extension_hob_by_guid(smbios_memory_info_guid, size); -} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index eeca491..e7778ec 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -74,7 +74,6 @@ void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); -const void *fsp_find_smbios_memory_info(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); void fsp_display_fvi_version_hob(void); diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index b79abb0..f09f45b 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -21,6 +21,12 @@ #include <soc/meminit.h> #include <string.h> +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \ + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \ +} + void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) { int channel, dimm, dimm_max, index; @@ -30,6 +36,8 @@ struct memory_info *mem_info; const CHANNEL_INFO *channel_info; const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; if (mem_sku >= lp4cfg->num_skus) { printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", @@ -37,7 +45,15 @@ return; } - memory_info_hob = fsp_find_smbios_memory_info(&hob_size); + /* Locate the memory info HOB */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS memory info HOB is missing\n"); + return; + } /* * Allocate CBMEM area for DIMM information used to populate SMBIOS diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 20e7cd2..21b09af 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -21,6 +21,12 @@ #include <soc/meminit.h> #include <string.h> +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \ + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \ +} + void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) { int channel, dimm, dimm_max, index, node; @@ -31,15 +37,20 @@ const CHANNEL_INFO *channel_info; const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; const CONTROLLER_INFO *ctrl_info; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; if (mem_sku >= lp4cfg->num_skus) { printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", mem_sku, lp4cfg->num_skus); return; } + /* Locate the memory info HOB */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); - memory_info_hob = fsp_find_smbios_memory_info(&hob_size); - if (memory_info_hob == NULL) { + if (memory_info_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS memory info HOB is missing\n"); return; } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index e0286f3..f675933 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -30,6 +30,12 @@ void __attribute__((weak)) mainboard_config_gpios(void) {} +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, \ + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 \ +} + #if IS_ENABLED(CONFIG_DISPLAY_HOBS) static void display_fsp_smbios_memory_info_hob(void) { @@ -38,51 +44,56 @@ const DIMM_INFO *dimm_info; const CHANNEL_INFO *channel_info; const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; /* Locate the memory info HOB */ - memory_info_hob = fsp_find_smbios_memory_info(&hob_size); + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ - if (memory_info_hob) { - printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); - printk(BIOS_DEBUG, " 0x%02x: Revision\n", - memory_info_hob->Revision); - printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", - memory_info_hob->MemoryType); - printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", - memory_info_hob->MemoryFrequencyInMHz); - printk(BIOS_DEBUG, " %d: DataWidth in bits\n", - memory_info_hob->DataWidth); - printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", - memory_info_hob->ErrorCorrectionType); - printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", - memory_info_hob->ChannelCount); - for (channel = 0; channel < memory_info_hob->ChannelCount; - channel++) { - channel_info = &memory_info_hob->ChannelInfo[channel]; - printk(BIOS_DEBUG, " Channel %d\n", channel); - printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", - channel_info->ChannelId); - printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", - channel_info->DimmCount); - for (dimm = 0; dimm < channel_info->DimmCount; - dimm++) { - dimm_info = &channel_info->DimmInfo[dimm]; - printk(BIOS_DEBUG, " DIMM %d\n", dimm); - printk(BIOS_DEBUG, " 0x%02x: DimmId\n", - dimm_info->DimmId); - printk(BIOS_DEBUG, " %d: SizeInMb\n", - dimm_info->SizeInMb); - printk(BIOS_DEBUG, " 0x%04x: MfgId\n", - dimm_info->MfgId); - printk(BIOS_DEBUG, "%*.*s: ModulePartNum\n", - (int)sizeof(dimm_info->ModulePartNum), - (int)sizeof(dimm_info->ModulePartNum), - dimm_info->ModulePartNum); - } + printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); + printk(BIOS_DEBUG, " 0x%02x: Revision\n", + memory_info_hob->Revision); + printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", + memory_info_hob->MemoryType); + printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", + memory_info_hob->MemoryFrequencyInMHz); + printk(BIOS_DEBUG, " %d: DataWidth in bits\n", + memory_info_hob->DataWidth); + printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", + memory_info_hob->ErrorCorrectionType); + printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", + memory_info_hob->ChannelCount); + for (channel = 0; channel < memory_info_hob->ChannelCount; + channel++) { + channel_info = &memory_info_hob->ChannelInfo[channel]; + printk(BIOS_DEBUG, " Channel %d\n", channel); + printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", + channel_info->ChannelId); + printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", + channel_info->DimmCount); + for (dimm = 0; dimm < channel_info->DimmCount; + dimm++) { + dimm_info = &channel_info->DimmInfo[dimm]; + printk(BIOS_DEBUG, " DIMM %d\n", dimm); + printk(BIOS_DEBUG, " 0x%02x: DimmId\n", + dimm_info->DimmId); + printk(BIOS_DEBUG, " %d: SizeInMb\n", + dimm_info->SizeInMb); + printk(BIOS_DEBUG, " 0x%04x: MfgId\n", + dimm_info->MfgId); + printk(BIOS_DEBUG, "%*.*s: ModulePartNum\n", + (int)sizeof(dimm_info->ModulePartNum), + (int)sizeof(dimm_info->ModulePartNum), + dimm_info->ModulePartNum); } - } else { - printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB not found!!!\n"); } } #endif -- To view, visit https://review.coreboot.org/23650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Gerrit-Change-Number: 23650 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/lenovo/w520: Add ThinkPad W520 support
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23564 ) Change subject: mb/lenovo/w520: Add ThinkPad W520 support ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67194/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21750/ : SUCCESS -- To view, visit https://review.coreboot.org/23564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Gerrit-Change-Number: 23564 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Rikken <nico(a)nicorikken.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Rikken <nico(a)nicorikken.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 10:26:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801ix: Use common RCBA code
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23288 ) Change subject: sb/intel/i82801ix: Use common RCBA code ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67192/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21749/ : SUCCESS -- To view, visit https://review.coreboot.org/23288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I56a1dbf9c364f040ffb110121b6a28494ddb8f90 Gerrit-Change-Number: 23288 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 10:16:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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