coreboot-gerrit February 2018

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23628 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67114/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21678/ : SUCCESS -- To view, visit https://review.coreboot.org/23628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I70477cfa314ed607b41b9096bc1b8664eff6baf0 Gerrit-Change-Number: 23628 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 23:16:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by build bot (Jenkins) (Code Review) 07 Feb '18

07 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23627 ) Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67113/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21677/ : SUCCESS -- To view, visit https://review.coreboot.org/23627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If577601d76ec4a90ab4eb99a7ff2c3fc0b72b730 Gerrit-Change-Number: 23627 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 23:10:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by Robert Reeves (Code Review) 07 Feb '18

07 Feb '18

Robert Reeves has uploaded this change for review. ( https://review.coreboot.org/23628 Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... mainboard/hp: Add HP Elitebook 8770w This is based on the code from the 8470p port. Tested on the quad core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics cards. Tested working with both Quadro K3000M and GTX 980M 8GB. Tested and working: - memory: 4G+4G+4G+4G - Linux (Debian Stretch with kernel 4.9.0) boot from SeaBIOS payload with graphics init disabled in coreboot. I allow SeaBIOS to load the VBIOS from the MXM. - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - VGA - Displayport - Audio - S3 with SeaBIOS 1.10.3, not working with 1.11 - Brightness and volume FN keys Change-Id: I70477cfa314ed607b41b9096bc1b8664eff6baf0 Signed-off-by: xiinc37 <xiinc37(a)gmail.com> --- M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/8770w/board_info.txt M src/mainboard/hp/8770w/cmos.layout M src/mainboard/hp/8770w/devicetree.cb D src/mainboard/hp/8770w/gma-mainboard.ads M src/mainboard/hp/8770w/gpio.c M src/mainboard/hp/8770w/hda_verb.c M src/mainboard/hp/8770w/mainboard.c M src/mainboard/hp/8770w/romstage.c 9 files changed, 59 insertions(+), 151 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23628/1 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 2157867..c650309 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -13,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_HP_8470P +if BOARD_HP_8770W config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -23,13 +24,10 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_INTERNAL_IS_LVDS select EC_HP_KBC1126 select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE @@ -45,23 +43,15 @@ config MAINBOARD_DIR string - default hp/8470p + default hp/8770w config MAINBOARD_PART_NUMBER string - default "EliteBook 8470p" - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config VGA_BIOS_ID - string - default "8086,0166" + default "EliteBook 8770w" config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x179b + default 0x176c config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt index 1d0ca8b..0d04ad0 100644 --- a/src/mainboard/hp/8770w/board_info.txt +++ b/src/mainboard/hp/8770w/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/… ROM protocol: SPI ROM package: SOIC-16 ROM socketed: n diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout index f55fbd5..69d2767 100644 --- a/src/mainboard/hp/8770w/cmos.layout +++ b/src/mainboard/hp/8770w/cmos.layout @@ -3,6 +3,7 @@ ## ## Copyright (C) 2007-2008 coresystems GmbH ## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2018 Robert Reeves ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -64,7 +65,6 @@ #424 8 r 0 unused # coreboot config options: northbridge -432 3 e 11 gfx_uma_size #435 5 r 0 unused 440 8 h 0 volume @@ -88,27 +88,20 @@ 2 1 Disable 4 0 Fallback 4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew 7 0 Disable 7 1 Enable 7 2 Keep 9 0 AHCI 9 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index b7254bb..2f2a5e0 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,21 +16,6 @@ # chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.link_frequency_270_mhz" = "1" - register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000385" - register "gpu_dp_b_hotplug" = "4" - register "gpu_dp_c_hotplug" = "4" - register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" - register "gpu_panel_power_backlight_off_delay" = "2000" - register "gpu_panel_power_backlight_on_delay" = "2000" - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_down_delay" = "230" - register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on @@ -48,15 +34,15 @@ end device domain 0x0 on device pci 00.0 on # Host bridge - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 01.0 on # PCIe Bridge for discrete graphics end - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x103c 0x179b + device pci 02.0 off # Internal graphics VGA controller + subsystemid 0x103c 0x176c end - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x007c0201" @@ -68,7 +54,7 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x3b" + register "sata_port_map" = "0x1f" register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" @@ -77,40 +63,40 @@ register "spi_lvscc" = "0" device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 16.1 off # Management Engine Interface 2 end device pci 16.2 off # Management Engine IDE-R end device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end - device pci 1c.1 on # PCIe Port #2, ExpressCard - subsystemid 0x103c 0x179b + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x176c end - device pci 1c.2 on # PCIe Port #3, SD/MMC - subsystemid 0x103c 0x179b + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x176c end - device pci 1c.3 on # PCIe Port #4, WLAN - subsystemid 0x103c 0x179b + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x176c end - device pci 1c.4 off # PCIe Port #5 + device pci 1c.4 on # PCIe Port #5 end device pci 1c.5 off # PCIe Port #6 end @@ -119,12 +105,12 @@ device pci 1c.7 off # PCIe Port #8 end device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1e.0 off # PCI bridge end device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -146,7 +132,7 @@ end #chip superio/smsc/lpc47n217 end device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x179b + subsystemid 0x103c 0x176c end device pci 1f.3 off # SMBus end diff --git a/src/mainboard/hp/8770w/gma-mainboard.ads b/src/mainboard/hp/8770w/gma-mainboard.ads deleted file mode 100644 index da495f6..0000000 --- a/src/mainboard/hp/8770w/gma-mainboard.ads +++ /dev/null @@ -1,34 +0,0 @@ --- --- Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - Internal, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c index 768af5c..ac054d9 100644 --- a/src/mainboard/hp/8770w/gpio.c +++ b/src/mainboard/hp/8770w/gpio.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -18,7 +19,7 @@ #include <southbridge/intel/common/gpio.h> static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, + .gpio0 = GPIO_MODE_NATIVE, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -32,28 +33,27 @@ .gpio11 = GPIO_MODE_GPIO, .gpio12 = GPIO_MODE_NATIVE, .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, .gpio15 = GPIO_MODE_GPIO, .gpio16 = GPIO_MODE_GPIO, .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, .gpio22 = GPIO_MODE_GPIO, .gpio23 = GPIO_MODE_GPIO, .gpio24 = GPIO_MODE_GPIO, .gpio25 = GPIO_MODE_NATIVE, .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_NATIVE, .gpio29 = GPIO_MODE_GPIO, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_NATIVE, }; static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, .gpio3 = GPIO_DIR_INPUT, @@ -64,29 +64,23 @@ .gpio10 = GPIO_DIR_INPUT, .gpio11 = GPIO_DIR_OUTPUT, .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, .gpio15 = GPIO_DIR_INPUT, .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_OUTPUT, - .gpio21 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_OUTPUT, .gpio23 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_OUTPUT, .gpio29 = GPIO_DIR_OUTPUT, }; static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, .gpio8 = GPIO_LEVEL_LOW, .gpio11 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_HIGH, .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, .gpio29 = GPIO_LEVEL_HIGH, }; @@ -102,7 +96,6 @@ .gpio7 = GPIO_INVERT, .gpio10 = GPIO_INVERT, .gpio13 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, }; static const struct pch_gpio_set1 pch_gpio_set1_blink = { @@ -112,9 +105,9 @@ .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_GPIO, - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, .gpio38 = GPIO_MODE_GPIO, .gpio39 = GPIO_MODE_GPIO, .gpio40 = GPIO_MODE_NATIVE, @@ -126,7 +119,7 @@ .gpio46 = GPIO_MODE_GPIO, .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_GPIO, - .gpio49 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, .gpio50 = GPIO_MODE_GPIO, .gpio51 = GPIO_MODE_GPIO, .gpio52 = GPIO_MODE_GPIO, @@ -146,15 +139,11 @@ static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_OUTPUT, - .gpio37 = GPIO_DIR_OUTPUT, .gpio38 = GPIO_DIR_INPUT, .gpio39 = GPIO_DIR_INPUT, .gpio44 = GPIO_DIR_INPUT, .gpio46 = GPIO_DIR_OUTPUT, .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_OUTPUT, .gpio50 = GPIO_DIR_INPUT, .gpio51 = GPIO_DIR_INPUT, .gpio52 = GPIO_DIR_INPUT, @@ -168,11 +157,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, .gpio46 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio57 = GPIO_LEVEL_HIGH, .gpio60 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c index 0d7389a..51869cb 100644 --- a/src/mainboard/hp/8770w/hda_verb.c +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -4,6 +4,7 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,11 +20,11 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c17c2, /* Subsystem ID */ + 0x103c176c, /* Subsystem ID */ 0x0000000b, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x103c17c2), + AZALIA_SUBVENDOR(0x0, 0x103c176c), /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), @@ -54,21 +55,6 @@ /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - - 0x00000004, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ - AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c index b5fdecc..9e2634f 100644 --- a/src/mainboard/hp/8770w/mainboard.c +++ b/src/mainboard/hp/8770w/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,13 +15,10 @@ */ #include <device/device.h> -#include <drivers/intel/gma/int15.h> static void mainboard_enable(device_t dev) { - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index bb9298c..f00c6f2 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -37,8 +38,9 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } -void mainboard_rcba_config(void) +void rcba_config(void) { + RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -76,5 +78,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); } -- To view, visit https://review.coreboot.org/23628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I70477cfa314ed607b41b9096bc1b8664eff6baf0 Gerrit-Change-Number: 23628 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com>

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 8770w
by Robert Reeves (Code Review) 07 Feb '18

07 Feb '18

Robert Reeves has uploaded this change for review. ( https://review.coreboot.org/23627 Change subject: mainboard/hp: Add HP Elitebook 8770w ...................................................................... mainboard/hp: Add HP Elitebook 8770w Code copied from the 8470p port. Change-Id: If577601d76ec4a90ab4eb99a7ff2c3fc0b72b730 Signed-off-by: xiinc37 <xiinc37(a)gmail.com> --- M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/8770w/board_info.txt M src/mainboard/hp/8770w/cmos.layout M src/mainboard/hp/8770w/devicetree.cb A src/mainboard/hp/8770w/gma-mainboard.ads M src/mainboard/hp/8770w/gpio.c M src/mainboard/hp/8770w/hda_verb.c M src/mainboard/hp/8770w/mainboard.c M src/mainboard/hp/8770w/romstage.c 9 files changed, 151 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23627/1 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index c650309..2157867 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -2,7 +2,6 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> -# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -14,7 +13,7 @@ # GNU General Public License for more details. # -if BOARD_HP_8770W +if BOARD_HP_8470P config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -24,10 +23,13 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS select EC_HP_KBC1126 select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE @@ -43,15 +45,23 @@ config MAINBOARD_DIR string - default hp/8770w + default hp/8470p config MAINBOARD_PART_NUMBER string - default "EliteBook 8770w" + default "EliteBook 8470p" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x176c + default 0x179b config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt index 0d04ad0..1d0ca8b 100644 --- a/src/mainboard/hp/8770w/board_info.txt +++ b/src/mainboard/hp/8770w/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/… +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 ROM protocol: SPI ROM package: SOIC-16 ROM socketed: n diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout index 69d2767..f55fbd5 100644 --- a/src/mainboard/hp/8770w/cmos.layout +++ b/src/mainboard/hp/8770w/cmos.layout @@ -3,7 +3,6 @@ ## ## Copyright (C) 2007-2008 coresystems GmbH ## Copyright (C) 2014 Vladimir Serbinenko -## Copyright (C) 2018 Robert Reeves ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -65,6 +64,7 @@ #424 8 r 0 unused # coreboot config options: northbridge +432 3 e 11 gfx_uma_size #435 5 r 0 unused 440 8 h 0 volume @@ -88,20 +88,27 @@ 2 1 Disable 4 0 Fallback 4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew 7 0 Disable 7 1 Enable 7 2 Keep 9 0 AHCI 9 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index 2f2a5e0..b7254bb 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -2,7 +2,6 @@ # This file is part of the coreboot project. # # Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> -# Copyright (C) 2018 Robert Reeves # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,6 +15,21 @@ # chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000385" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x0d9c0d9c" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on @@ -34,15 +48,15 @@ end device domain 0x0 on device pci 00.0 on # Host bridge - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 01.0 on # PCIe Bridge for discrete graphics end - device pci 02.0 off # Internal graphics VGA controller - subsystemid 0x103c 0x176c + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x179b end - chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x007c0201" @@ -54,7 +68,7 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x1f" + register "sata_port_map" = "0x3b" register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" @@ -63,40 +77,40 @@ register "spi_lvscc" = "0" device pci 14.0 on # USB 3.0 Controller - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 16.0 on # Management Engine Interface 1 - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 16.1 off # Management Engine Interface 2 end device pci 16.2 off # Management Engine IDE-R end device pci 16.3 on # Management Engine KT - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 1a.0 on # USB2 EHCI #2 - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 1b.0 on # High Definition Audio Audio controller - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 1c.0 on # PCIe Port #1 - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end - device pci 1c.1 on # PCIe Port #2 - subsystemid 0x103c 0x176c + device pci 1c.1 on # PCIe Port #2, ExpressCard + subsystemid 0x103c 0x179b end - device pci 1c.2 on # PCIe Port #3 - subsystemid 0x103c 0x176c + device pci 1c.2 on # PCIe Port #3, SD/MMC + subsystemid 0x103c 0x179b end - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x103c 0x176c + device pci 1c.3 on # PCIe Port #4, WLAN + subsystemid 0x103c 0x179b end - device pci 1c.4 on # PCIe Port #5 + device pci 1c.4 off # PCIe Port #5 end device pci 1c.5 off # PCIe Port #6 end @@ -105,12 +119,12 @@ device pci 1c.7 off # PCIe Port #8 end device pci 1d.0 on # USB2 EHCI #1 - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 1e.0 off # PCI bridge end device pci 1f.0 on # LPC bridge PCI-LPC bridge - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b chip ec/hp/kbc1126 register "ec_data_port" = "0x62" register "ec_cmd_port" = "0x66" @@ -132,7 +146,7 @@ end #chip superio/smsc/lpc47n217 end device pci 1f.2 on # SATA Controller 1 - subsystemid 0x103c 0x176c + subsystemid 0x103c 0x179b end device pci 1f.3 off # SMBus end diff --git a/src/mainboard/hp/8770w/gma-mainboard.ads b/src/mainboard/hp/8770w/gma-mainboard.ads new file mode 100644 index 0000000..da495f6 --- /dev/null +++ b/src/mainboard/hp/8770w/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c index ac054d9..768af5c 100644 --- a/src/mainboard/hp/8770w/gpio.c +++ b/src/mainboard/hp/8770w/gpio.c @@ -3,7 +3,6 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,7 +18,7 @@ #include <southbridge/intel/common/gpio.h> static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NATIVE, + .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -33,27 +32,28 @@ .gpio11 = GPIO_MODE_GPIO, .gpio12 = GPIO_MODE_NATIVE, .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, .gpio15 = GPIO_MODE_GPIO, .gpio16 = GPIO_MODE_GPIO, .gpio17 = GPIO_MODE_GPIO, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, .gpio22 = GPIO_MODE_GPIO, .gpio23 = GPIO_MODE_GPIO, .gpio24 = GPIO_MODE_GPIO, .gpio25 = GPIO_MODE_NATIVE, .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_NATIVE, + .gpio28 = GPIO_MODE_GPIO, .gpio29 = GPIO_MODE_GPIO, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_NATIVE, }; static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, .gpio3 = GPIO_DIR_INPUT, @@ -64,23 +64,29 @@ .gpio10 = GPIO_DIR_INPUT, .gpio11 = GPIO_DIR_OUTPUT, .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, .gpio15 = GPIO_DIR_INPUT, .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_OUTPUT, .gpio23 = GPIO_DIR_INPUT, .gpio24 = GPIO_DIR_OUTPUT, .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, .gpio29 = GPIO_DIR_OUTPUT, }; static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, .gpio8 = GPIO_LEVEL_LOW, .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_HIGH, .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, .gpio29 = GPIO_LEVEL_HIGH, }; @@ -96,6 +102,7 @@ .gpio7 = GPIO_INVERT, .gpio10 = GPIO_INVERT, .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, }; static const struct pch_gpio_set1 pch_gpio_set1_blink = { @@ -105,9 +112,9 @@ .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_NATIVE, - .gpio36 = GPIO_MODE_NATIVE, - .gpio37 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, .gpio38 = GPIO_MODE_GPIO, .gpio39 = GPIO_MODE_GPIO, .gpio40 = GPIO_MODE_NATIVE, @@ -119,7 +126,7 @@ .gpio46 = GPIO_MODE_GPIO, .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_GPIO, - .gpio49 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, .gpio50 = GPIO_MODE_GPIO, .gpio51 = GPIO_MODE_GPIO, .gpio52 = GPIO_MODE_GPIO, @@ -139,11 +146,15 @@ static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, .gpio38 = GPIO_DIR_INPUT, .gpio39 = GPIO_DIR_INPUT, .gpio44 = GPIO_DIR_INPUT, .gpio46 = GPIO_DIR_OUTPUT, .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, .gpio50 = GPIO_DIR_INPUT, .gpio51 = GPIO_DIR_INPUT, .gpio52 = GPIO_DIR_INPUT, @@ -157,7 +168,11 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, .gpio46 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio57 = GPIO_LEVEL_HIGH, .gpio60 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c index 51869cb..0d7389a 100644 --- a/src/mainboard/hp/8770w/hda_verb.c +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -4,7 +4,6 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> - * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,11 +19,11 @@ const u32 cim_verb_data[] = { 0x111d7605, /* Codec Vendor / Device ID: IDT */ - 0x103c176c, /* Subsystem ID */ + 0x103c17c2, /* Subsystem ID */ 0x0000000b, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x103c176c), + AZALIA_SUBVENDOR(0x0, 0x103c17c2), /* NID 0x0a. */ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), @@ -55,6 +54,21 @@ /* NID 0x20. */ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c index 9e2634f..b5fdecc 100644 --- a/src/mainboard/hp/8770w/mainboard.c +++ b/src/mainboard/hp/8770w/mainboard.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> - * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,10 +14,13 @@ */ #include <device/device.h> +#include <drivers/intel/gma/int15.h> static void mainboard_enable(device_t dev) { - + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index f00c6f2..bb9298c 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> - * Copyright (C) 2018 Robert Reeves * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,9 +37,8 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } -void rcba_config(void) +void mainboard_rcba_config(void) { - RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -78,7 +76,5 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); } -- To view, visit https://review.coreboot.org/23627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If577601d76ec4a90ab4eb99a7ff2c3fc0b72b730 Gerrit-Change-Number: 23627 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Reeves <xiinc37(a)gmail.com>

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Change in coreboot[master]: mainboard/google/meowth: Limit Package PL2 to 11.625W
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23581 ) Change subject: mainboard/google/meowth: Limit Package PL2 to 11.625W ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67108/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21672/ : SUCCESS -- To view, visit https://review.coreboot.org/23581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 Gerrit-Change-Number: 23581 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 22:20:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add Pch iSCLK programming
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23367 ) Change subject: soc/intel/cannonlake: Add Pch iSCLK programming ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67112/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21676/ : SUCCESS -- To view, visit https://review.coreboot.org/23367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6 Gerrit-Change-Number: 23367 Gerrit-PatchSet: 11 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 22:16:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: enable PCH iSCLK
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23368 ) Change subject: mainboard/google/meowth: enable PCH iSCLK ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67111/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21675/ : SUCCESS -- To view, visit https://review.coreboot.org/23368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa Gerrit-Change-Number: 23368 Gerrit-PatchSet: 11 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 22:11:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: enable PCH iSCLK
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23368 ) Change subject: mainboard/google/meowth: enable PCH iSCLK ...................................................................... Patch Set 10: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67110/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21674/ : ABORTED -- To view, visit https://review.coreboot.org/23368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa Gerrit-Change-Number: 23368 Gerrit-PatchSet: 10 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 22:05:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: enable PCH iSCLK
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23368 ) Change subject: mainboard/google/meowth: enable PCH iSCLK ...................................................................... Patch Set 9: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67109/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21673/ : SUCCESS -- To view, visit https://review.coreboot.org/23368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa Gerrit-Change-Number: 23368 Gerrit-PatchSet: 9 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 22:04:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67106/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21670/ : SUCCESS -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 21:53:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018