coreboot-gerrit February 2018

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Change in coreboot[master]: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23540 ) Change subject: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67091/ : SUCCESS -- To view, visit https://review.coreboot.org/23540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22 Gerrit-Change-Number: 23540 Gerrit-PatchSet: 6 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 08:58:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/saddlebrook: Enable LPC IO Decode Range
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23620 ) Change subject: mb/intel/saddlebrook: Enable LPC IO Decode Range ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67090/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21657/ : SUCCESS -- To view, visit https://review.coreboot.org/23620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4fce91ac47efb3060ba641d8e06438ac4e50dd24 Gerrit-Change-Number: 23620 Gerrit-PatchSet: 2 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 08:54:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23264 ) Change subject: soc/intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67089/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21656/ : SUCCESS -- To view, visit https://review.coreboot.org/23264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib07d6aaf5694eb0641b6ac2fa89720b6bb5ed8cf Gerrit-Change-Number: 23264 Gerrit-PatchSet: 6 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 08:50:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: storage: Fix CMD13 failure issue
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23541 ) Change subject: storage: Fix CMD13 failure issue ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67088/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21655/ : SUCCESS -- To view, visit https://review.coreboot.org/23541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e Gerrit-Change-Number: 23541 Gerrit-PatchSet: 2 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 06 Feb 2018 08:38:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23540 ) Change subject: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67087/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21654/ : SUCCESS -- To view, visit https://review.coreboot.org/23540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22 Gerrit-Change-Number: 23540 Gerrit-PatchSet: 5 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 08:35:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23621 ) Change subject: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67086/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21653/ : SUCCESS -- To view, visit https://review.coreboot.org/23621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Gerrit-Change-Number: 23621 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 08:10:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
by Subrata Banik (Code Review) 06 Feb '18

06 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23621 Change subject: soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 ...................................................................... soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 This patch ensures to have Type 17 SMBIOS table for CannonLake Platform. TEST=Enable to get correct SMBIOS DIMM type information as per SMBIOS spec 3.1 Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/23621/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 8b3794f..111b671 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -24,14 +24,88 @@ #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> #include <memory_info.h> +#include <soc/intel/common/smbios.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <string.h> #include <timestamp.h> static struct chipset_power_state power_state CAR_GLOBAL; +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != 2) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + memory_info_hob->DataWidth); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + asmlinkage void car_stage_entry(void) { bool s3wake; @@ -49,6 +123,8 @@ timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + if (!s3wake) + save_dimm_info(); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); -- To view, visit https://review.coreboot.org/23621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Gerrit-Change-Number: 23621 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23264 ) Change subject: soc/intel/skylake: Add symbol SOC_IO_LPC_DECODE_ENABLE ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67085/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21652/ : SUCCESS -- To view, visit https://review.coreboot.org/23264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib07d6aaf5694eb0641b6ac2fa89720b6bb5ed8cf Gerrit-Change-Number: 23264 Gerrit-PatchSet: 5 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 07:28:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/saddlebrook: Enable LPC IO Decode Range
by Teo Boon Tiong (Code Review) 06 Feb '18

06 Feb '18

Teo Boon Tiong has posted comments on this change. ( https://review.coreboot.org/23620 ) Change subject: mb/intel/saddlebrook: Enable LPC IO Decode Range ...................................................................... Patch Set 1: Dependent on https://review.coreboot.org/#/c/coreboot/+/23264/ -- To view, visit https://review.coreboot.org/23620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4fce91ac47efb3060ba641d8e06438ac4e50dd24 Gerrit-Change-Number: 23620 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 07:15:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/saddlebrook: Enable LPC IO Decode Range
by build bot (Jenkins) (Code Review) 06 Feb '18

06 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23620 ) Change subject: mb/intel/saddlebrook: Enable LPC IO Decode Range ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67084/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/21651/ : SUCCESS -- To view, visit https://review.coreboot.org/23620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4fce91ac47efb3060ba641d8e06438ac4e50dd24 Gerrit-Change-Number: 23620 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Feb 2018 07:06:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018