coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add missing GPIO pin definitions
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22482 ) Change subject: soc/intel/cannonlake: Add missing GPIO pin definitions ...................................................................... Patch Set 22: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67246/ : UNSTABLE -- To view, visit https://review.coreboot.org/22482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Gerrit-Change-Number: 22482 Gerrit-PatchSet: 22 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 23:49:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/intel/cannonlake: Add gpio groups
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22572 ) Change subject: src/soc/intel/cannonlake: Add gpio groups ...................................................................... Patch Set 15: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67247/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21797/ : SUCCESS -- To view, visit https://review.coreboot.org/22572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I00be5e9bf25f1723a3d9e177588135d63ab89662 Gerrit-Change-Number: 22572 Gerrit-PatchSet: 15 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 23:43:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add missing GPIO pin definitions
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22482 ) Change subject: soc/intel/cannonlake: Add missing GPIO pin definitions ...................................................................... Patch Set 21: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67245/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21796/ : ABORTED -- To view, visit https://review.coreboot.org/22482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Gerrit-Change-Number: 22482 Gerrit-PatchSet: 21 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 23:34:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add GPIO community 3 definition
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22482 ) Change subject: soc/intel/cannonlake: Add GPIO community 3 definition ...................................................................... Patch Set 20: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67244/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21795/ : ABORTED -- To view, visit https://review.coreboot.org/22482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Gerrit-Change-Number: 22482 Gerrit-PatchSet: 20 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 23:33:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23644 ) Change subject: soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67243/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21794/ : SUCCESS -- To view, visit https://review.coreboot.org/23644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b Gerrit-Change-Number: 23644 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 23:17:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/kontron/986lcd-m: Disable ethernet devices in ramstage
by Nico Huber (Code Review) 08 Feb '18

08 Feb '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23663 ) Change subject: mb/kontron/986lcd-m: Disable ethernet devices in ramstage ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/23663/1/src/mainboard/kontron/986lcd-m/main… File src/mainboard/kontron/986lcd-m/mainboard.c: https://review.coreboot.org/#/c/23663/1/src/mainboard/kontron/986lcd-m/main… PS1, Line 175: static void mainboard_enable(device_t dev) Isn't that far too late (when hiding/coalescing is handled in chip->init)? -- To view, visit https://review.coreboot.org/23663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8abc4c8289f5e34bbb7d5ee57d9a2f404e26189 Gerrit-Change-Number: 23663 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 22:54:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/kontron/986lcd-m: Disable ethernet devices in ramstage
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23663 ) Change subject: mb/kontron/986lcd-m: Disable ethernet devices in ramstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67242/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21793/ : SUCCESS -- To view, visit https://review.coreboot.org/23663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8abc4c8289f5e34bbb7d5ee57d9a2f404e26189 Gerrit-Change-Number: 23663 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 22:22:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801gx: Automatically handle disabling functions
by build bot (Jenkins) (Code Review) 08 Feb '18

08 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23662 ) Change subject: sb/intel/i82801gx: Automatically handle disabling functions ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67241/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21792/ : SUCCESS -- To view, visit https://review.coreboot.org/23662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2f6f270c631b97ececf1bd3c23f19b27828e6885 Gerrit-Change-Number: 23662 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 22:21:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801gx: Automatically handle disabling functions
by Arthur Heymans (Code Review) 08 Feb '18

08 Feb '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23662 ) Change subject: sb/intel/i82801gx: Automatically handle disabling functions ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/23662/4/src/mainboard/kontron/986lcd-m/roms… File src/mainboard/kontron/986lcd-m/romstage.c: https://review.coreboot.org/#/c/23662/4/src/mainboard/kontron/986lcd-m/roms… PS4, Line 221: reg32 |= 1; > Drop? not sure if this needs to be done on each FD write or once. anyway follow-up patch will move this to ramstage... https://review.coreboot.org/#/c/23662/4/src/southbridge/intel/i82801gx/i828… File src/southbridge/intel/i82801gx/i82801gx.c: https://review.coreboot.org/#/c/23662/4/src/southbridge/intel/i82801gx/i828… PS4, Line 43: BIOS_INFO, > It's not that bad, is it? leftover from i82801ix which dies here -- To view, visit https://review.coreboot.org/23662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2f6f270c631b97ececf1bd3c23f19b27828e6885 Gerrit-Change-Number: 23662 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2018 22:16:53 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/kontron/986lcd-m: Disable ethernet devices in ramstage
by Arthur Heymans (Code Review) 08 Feb '18

08 Feb '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23663 Change subject: mb/kontron/986lcd-m: Disable ethernet devices in ramstage ...................................................................... mb/kontron/986lcd-m: Disable ethernet devices in ramstage Move disabling PCIe ports and the respective ethernet port out of romstage. Change-Id: Ic8abc4c8289f5e34bbb7d5ee57d9a2f404e26189 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/romstage.c 2 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/23663/1 diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index d729533..5519f58 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -20,6 +20,8 @@ #include <pc80/mc146818rtc.h> #include <arch/io.h> #include <arch/interrupt.h> +#include <device/pci_def.h> +#include <string.h> /* Hardware Monitor */ @@ -148,6 +150,25 @@ hwm_write(0x40, 0x01); /* Init, but no SMI# */ } +static void disable_ethernet(void) +{ + struct device *dev; + int i; + + for (i = 0; i < 3; i++) { + char buffer[10]; + snprintf(buffer, sizeof(buffer), "ethernet%d", i + 1); + int disable_eth; + get_option(&disable_eth, buffer); + if (disable_eth) { + printk(BIOS_DEBUG, "Disabling ethernet adapter %d.\n", + i + 1); + dev = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + dev->enabled = 0; + } + } +} + /* mainboard_enable is executed as first thing after */ /* enumerate_buses(). */ @@ -155,6 +176,7 @@ { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); + disable_ethernet(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c356e5f..51a080a 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -183,8 +183,6 @@ static void rcba_config(void) { - u32 reg32; - /* Set up virtual channel 0 */ /* Device 1f interrupt pin register */ @@ -202,26 +200,6 @@ /* Enable IOAPIC */ RCBA8(OIC) = 0x03; - /* Disable unused devices */ - reg32 = 0; - - if (read_option(ethernet1, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); - reg32 |= FD_PCIE1; - } - if (read_option(ethernet2, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); - reg32 |= FD_PCIE2; - } - if (read_option(ethernet3, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); - reg32 |= FD_PCIE3; - } - - reg32 |= 1; - - RCBA32(FD) = reg32; - /* Enable PCIe Root Port Clock Gate */ } -- To view, visit https://review.coreboot.org/23663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8abc4c8289f5e34bbb7d5ee57d9a2f404e26189 Gerrit-Change-Number: 23663 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit February 2018