coreboot-gerrit February 2018

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Change in coreboot[master]: nb/intel/gm45: Get rid off device_t
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23667 ) Change subject: nb/intel/gm45: Get rid off device_t ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67262/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21812/ : SUCCESS -- To view, visit https://review.coreboot.org/23667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db Gerrit-Change-Number: 23667 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 06:55:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/gm45: Get rid off device_t
by Elyes HAOUAS (Code Review) 09 Feb '18

09 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23667 Change subject: nb/intel/gm45: Get rid off device_t ...................................................................... nb/intel/gm45: Get rid off device_t Use of `device_t` has been abandoned in ramstage Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/northbridge.c 4 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23667/1 diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index b90afca..73b098f 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; @@ -105,7 +105,7 @@ return current; } -unsigned long northbridge_write_acpi_tables(device_t device, +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp) { diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 34f734c..ecf7811 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -447,7 +447,7 @@ #include <device/device.h> struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); #endif #endif /* !__ACPI__ */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index bdad49b..db9fe1d 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -778,7 +778,7 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -793,7 +793,7 @@ const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); if (!dev) { return NULL; } @@ -801,7 +801,7 @@ return &chip->gfx; } -static void gma_ssdt(device_t device) +static void gma_ssdt(struct device *device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8215979..c6b9888 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -41,7 +41,7 @@ *base = 0; *len = 0; - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -68,7 +68,7 @@ return 0; } -static void mch_domain_read_resources(device_t dev) +static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0; @@ -161,7 +161,7 @@ } } -static void mch_domain_set_resources(device_t dev) +static void mch_domain_set_resources(struct device *dev) { struct resource *resource; int i; @@ -176,7 +176,7 @@ assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(struct device *dev) { u32 reg32; @@ -198,7 +198,7 @@ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -211,7 +211,7 @@ .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { -- To view, visit https://review.coreboot.org/23667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db Gerrit-Change-Number: 23667 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/kontron/986lcd-m: Disable ethernet devices in ramstage
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23663 ) Change subject: mb/kontron/986lcd-m: Disable ethernet devices in ramstage ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67261/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21811/ : SUCCESS -- To view, visit https://review.coreboot.org/23663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8abc4c8289f5e34bbb7d5ee57d9a2f404e26189 Gerrit-Change-Number: 23663 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 06:15:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/broadcom/secimage: Add distclean target
by Julius Werner (Code Review) 09 Feb '18

09 Feb '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/23666 ) Change subject: util/broadcom/secimage: Add distclean target ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/23666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953 Gerrit-Change-Number: 23666 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 03:25:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/broadcom/secimage: Add distclean target
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23666 ) Change subject: util/broadcom/secimage: Add distclean target ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67260/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21810/ : SUCCESS -- To view, visit https://review.coreboot.org/23666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953 Gerrit-Change-Number: 23666 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 03:22:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/broadcom/secimage: Add distclean target
by Martin Roth (Code Review) 09 Feb '18

09 Feb '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/23666 Change subject: util/broadcom/secimage: Add distclean target ...................................................................... util/broadcom/secimage: Add distclean target When running 'make distclean' on coreboot, the build cleans the tools as well. Since secimage didn't have a distclean target, it gave an error that the distclean target didn't exist. This didn't actually affect anything more than the secimage clean, but it was impossible to tell that from the warning: % make distclean make[1]: *** No rule to make target 'distclean'. Stop. Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/broadcom/secimage/Makefile 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/23666/1 diff --git a/util/broadcom/secimage/Makefile b/util/broadcom/secimage/Makefile index 132c59e..ab8a1a4 100644 --- a/util/broadcom/secimage/Makefile +++ b/util/broadcom/secimage/Makefile @@ -36,7 +36,7 @@ @find test -maxdepth 1 -type f -executable \ | xargs -I "{}" sh -c "{} $$(realpath $<)" -.PHONY: clean +.PHONY: clean distclean -clean: +clean distclean: $(RM) -f $(TARGET) $(OBJS) -- To view, visit https://review.coreboot.org/23666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953 Gerrit-Change-Number: 23666 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Put outl arguments in correct order
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23665 ) Change subject: soc/amd/stoneyridge: Put outl arguments in correct order ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67259/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21809/ : SUCCESS -- To view, visit https://review.coreboot.org/23665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869 Gerrit-Change-Number: 23665 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 03:14:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Put outl arguments in correct order
by Martin Roth (Code Review) 09 Feb '18

09 Feb '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/23665 Change subject: soc/amd/stoneyridge: Put outl arguments in correct order ...................................................................... soc/amd/stoneyridge: Put outl arguments in correct order outl takes value then port. BUG=b:72130849 Test=None Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/23665/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 7cc8900..2830d18 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -99,7 +99,7 @@ case APM_CNT_ACPI_DISABLE: reg32 = inl(ACPI_PM1_CNT_BLK); reg32 &= ~(1 << 0); /* clear SCI_EN */ - outl(ACPI_PM1_CNT_BLK, reg32); + outl(reg32, ACPI_PM1_CNT_BLK); break; case ELOG_GSMI_APM_CNT: if (IS_ENABLED(CONFIG_ELOG_GSMI)) -- To view, visit https://review.coreboot.org/23665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869 Gerrit-Change-Number: 23665 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: chromeec: Fix ACPI compile warning
by Nicolas Boichat (Code Review) 09 Feb '18

09 Feb '18

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/23661 ) Change subject: chromeec: Fix ACPI compile warning ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/23661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Gerrit-Change-Number: 23661 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 02:05:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: chromeec: Fix ACPI compile warning
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23661 ) Change subject: chromeec: Fix ACPI compile warning ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67258/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21808/ : SUCCESS -- To view, visit https://review.coreboot.org/23661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Gerrit-Change-Number: 23661 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 01:59:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018