coreboot-gerrit February 2018

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Change in coreboot[master]: nb/intel/fsp_rangeley: Get rid off device_t
by Elyes HAOUAS (Code Review) 09 Feb '18

09 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23671 Change subject: nb/intel/fsp_rangeley: Get rid off device_t ...................................................................... nb/intel/fsp_rangeley: Get rid off device_t Use of `device_t` has been abandoned in ramstage Change-Id: I0b969a5109276d108e6140bad338c74786b967f3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_rangeley/northbridge.h 3 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/23671/1 diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 00947aa..c8e6d45 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -30,7 +30,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; @@ -61,7 +61,7 @@ return current; } -void northbridge_acpi_fill_ssdt_generator(device_t device) +void northbridge_acpi_fill_ssdt_generator(struct device *device) { u32 bmbound; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 0134eff..22e6cee 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -59,7 +59,7 @@ static int get_pcie_bar(u32 *base) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -94,7 +94,7 @@ return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -139,7 +139,7 @@ index = add_fixed_resources(dev, index); } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { u32 pcie_config_base; int buses; @@ -158,7 +158,7 @@ mc_add_dram_resources(dev); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { /* * Assign memory resources for PCI devices @@ -168,13 +168,13 @@ assign_resources(dev->link_list); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device *dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -189,7 +189,7 @@ { } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device *dev) { } @@ -239,7 +239,7 @@ .devices = pci_device_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -252,7 +252,7 @@ .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index ba4cfdd..f68d175 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -73,7 +73,7 @@ void report_platform_info(void); #ifndef __SIMPLE_DEVICE__ -void northbridge_acpi_fill_ssdt_generator(device_t device); +void northbridge_acpi_fill_ssdt_generator(struct device *device); #endif #endif /* #ifndef __ASSEMBLER__ */ -- To view, visit https://review.coreboot.org/23671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0b969a5109276d108e6140bad338c74786b967f3 Gerrit-Change-Number: 23671 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acp...
by Kaiyen Chang (Code Review) 09 Feb '18

09 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23670 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_t ...................................................................... mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_t This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang(a)intel.com> --- M src/mainboard/google/poppy/variants/nami/nhlt.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/23670/2 -- To view, visit https://review.coreboot.org/23670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Gerrit-Change-Number: 23670 Gerrit-PatchSet: 2 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/haswell: Get rid off device_t
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23669 ) Change subject: nb/intel/haswell: Get rid off device_t ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67265/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21815/ : SUCCESS -- To view, visit https://review.coreboot.org/23669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica914a76f4638621e12441adb29731ab078d8bee Gerrit-Change-Number: 23669 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 07:38:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acp...
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23670 ) Change subject: mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_t ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67266/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/21816/ : SUCCESS -- To view, visit https://review.coreboot.org/23670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Gerrit-Change-Number: 23670 Gerrit-PatchSet: 1 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 07:36:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acp...
by Kaiyen Chang (Code Review) 09 Feb '18

09 Feb '18

Kaiyen Chang has uploaded this change for review. ( https://review.coreboot.org/23670 Change subject: mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_t ...................................................................... mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_t This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang(a)intel.com> --- M src/mainboard/google/poppy/variants/nami/nhlt.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/23670/1 diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c index 690fed5..7731650 100644 --- a/src/mainboard/google/poppy/variants/nami/nhlt.c +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -33,3 +33,12 @@ printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); } + +void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "NAMIMAX"; + *oem_revision = 0; +} + -- To view, visit https://review.coreboot.org/23670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Gerrit-Change-Number: 23670 Gerrit-PatchSet: 1 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com>

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Change in coreboot[master]: nb/intel/haswell: Get rid off device_t
by Elyes HAOUAS (Code Review) 09 Feb '18

09 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23669 Change subject: nb/intel/haswell: Get rid off device_t ...................................................................... nb/intel/haswell: Get rid off device_t Use of `device_t` has been abandoned in ramstage Change-Id: Ica914a76f4638621e12441adb29731ab078d8bee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/23669/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index e032948..d8ac4e2 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -25,7 +25,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c7319fb..3a348d2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -487,7 +487,7 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -501,7 +501,7 @@ const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); if (!dev) { return NULL; } @@ -509,7 +509,7 @@ return &chip->gfx; } -static void gma_ssdt(device_t device) +static void gma_ssdt(struct device *device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 9e7ce0e..6c528da 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,7 +103,7 @@ } } -static void minihd_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void minihd_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 32be916..68cc647 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -33,7 +33,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; u32 mask; @@ -69,7 +69,7 @@ return 0; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -125,7 +125,7 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -145,7 +145,7 @@ * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -202,7 +202,7 @@ const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; @@ -270,7 +270,7 @@ [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -278,7 +278,7 @@ } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -289,7 +289,7 @@ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -381,7 +381,7 @@ #endif } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -393,7 +393,7 @@ mc_add_dram_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -457,7 +457,7 @@ .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { bsp_init_and_start_aps(dev->link_list); } @@ -470,7 +470,7 @@ .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { -- To view, visit https://review.coreboot.org/23669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ica914a76f4638621e12441adb29731ab078d8bee Gerrit-Change-Number: 23669 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: nb/intel/sandybridge: Get rid off device_t
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23668 ) Change subject: nb/intel/sandybridge: Get rid off device_t ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67264/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21814/ : SUCCESS -- To view, visit https://review.coreboot.org/23668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I585aa48b99f4ef63905cab5d6d1502bfed0e6e42 Gerrit-Change-Number: 23668 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 07:31:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: nb/intel/sandybridge: Get rid off device_t
by Elyes HAOUAS (Code Review) 09 Feb '18

09 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23668 Change subject: nb/intel/sandybridge: Get rid off device_t ...................................................................... nb/intel/sandybridge: Get rid off device_t Use of `device_t` has been abandoned in ramstage Change-Id: I585aa48b99f4ef63905cab5d6d1502bfed0e6e42 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/23668/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 74aabf9..201498a 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -662,7 +662,7 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -676,7 +676,7 @@ const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); if (!dev) { return NULL; } @@ -684,7 +684,7 @@ return &chip->gfx; } -static void gma_ssdt(device_t device) +static void gma_ssdt(struct device *device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { @@ -729,7 +729,7 @@ static void gma_func0_disable(struct device *dev) { u16 reg16; - device_t dev_host = dev_find_slot(0, PCI_DEVFN(0,0)); + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0,0)); reg16 = pci_read_config16(dev_host, GGC); reg16 |= (1 << 1); /* disable VGA decode */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 9fed17e..322e4b8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -62,7 +62,7 @@ static int get_pcie_bar(u32 *base) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -120,7 +120,7 @@ } } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -273,7 +273,7 @@ .acpi_name = northbridge_acpi_name, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { u32 pcie_config_base; int buses; @@ -287,7 +287,7 @@ } } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -457,7 +457,7 @@ MCHBAR32(0x5500) = 0x00100001; } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -469,7 +469,7 @@ u32 northbridge_get_tseg_base(void) { - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); return northbridge_get_base_reg(dev, TSEG); } @@ -523,7 +523,7 @@ .device = 0x0158, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -536,7 +536,7 @@ .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8bbfae9..3d21d89 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -228,7 +228,7 @@ #include <device/device.h> struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); #endif #endif -- To view, visit https://review.coreboot.org/23668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I585aa48b99f4ef63905cab5d6d1502bfed0e6e42 Gerrit-Change-Number: 23668 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: nb/intel/gm45: Get rid off device_t
by build bot (Jenkins) (Code Review) 09 Feb '18

09 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23667 ) Change subject: nb/intel/gm45: Get rid off device_t ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67263/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21813/ : SUCCESS -- To view, visit https://review.coreboot.org/23667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db Gerrit-Change-Number: 23667 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Feb 2018 07:15:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/gm45: Get rid off device_t
by Elyes HAOUAS (Code Review) 09 Feb '18

09 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23667 to look at the new patch set (#2). Change subject: nb/intel/gm45: Get rid off device_t ...................................................................... nb/intel/gm45: Get rid off device_t Use of `device_t` has been abandoned in ramstage Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/northbridge.c 4 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23667/2 -- To view, visit https://review.coreboot.org/23667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db Gerrit-Change-Number: 23667 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit February 2018